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<html><head><title>NASM Manual</title></head>
<body><h1 align=center>The Netwide Assembler: NASM</h1>
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<h2><a name="chapter-5">Chapter 5: Standard Macro Packages</a></h2>
<p>The <code><nobr>%use</nobr></code> directive (see
<a href="nasmdoc4.html#section-4.6.4">section 4.6.4</a>) includes one of
the standard macro packages included with the NASM distribution and
compiled into the NASM binary. It operates like the
<code><nobr>%include</nobr></code> directive (see
<a href="nasmdoc4.html#section-4.6.1">section 4.6.1</a>), but the included
contents is provided by NASM itself.
<p>The names of standard macro packages are case insensitive, and can be
quoted or not.
<h3><a name="section-5.1">5.1 <code><nobr>altreg</nobr></code>: Alternate Register Names</a></h3>
<p>The <code><nobr>altreg</nobr></code> standard macro package provides
alternate register names. It provides numeric register names for all
registers (not just
<code><nobr>R8</nobr></code>-<code><nobr>R15</nobr></code>), the
Intel-defined aliases
<code><nobr>R8L</nobr></code>-<code><nobr>R15L</nobr></code> for the low
bytes of register (as opposed to the NASM/AMD standard names
<code><nobr>R8B</nobr></code>-<code><nobr>R15B</nobr></code>), and the
names <code><nobr>R0H</nobr></code>-<code><nobr>R3H</nobr></code> (by
analogy with <code><nobr>R0L</nobr></code>-<code><nobr>R3L</nobr></code>)
for <code><nobr>AH</nobr></code>, <code><nobr>CH</nobr></code>,
<code><nobr>DH</nobr></code>, and <code><nobr>BH</nobr></code>.
<p>Example use:
<p><pre>
%use altreg
proc:
mov r0l,r3h ; mov al,bh
ret
</pre>
<p>See also <a href="nasmdo11.html#section-11.1">section 11.1</a>.
<h3><a name="section-5.2">5.2 <code><nobr>smartalign</nobr></code>: Smart <code><nobr>ALIGN</nobr></code> Macro</a></h3>
<p>The <code><nobr>smartalign</nobr></code> standard macro package provides
for an <code><nobr>ALIGN</nobr></code> macro which is more powerful than
the default (and backwards-compatible) one (see
<a href="nasmdoc4.html#section-4.11.12">section 4.11.12</a>). When the
<code><nobr>smartalign</nobr></code> package is enabled, when
<code><nobr>ALIGN</nobr></code> is used without a second argument, NASM
will generate a sequence of instructions more efficient than a series of
<code><nobr>NOP</nobr></code>. Furthermore, if the padding exceeds a
specific threshold, then NASM will generate a jump over the entire padding
sequence.
<p>The specific instructions generated can be controlled with the new
<code><nobr>ALIGNMODE</nobr></code> macro. This macro takes two parameters:
one mode, and an optional jump threshold override. The modes are as
follows:
<ul>
<li><code><nobr>generic</nobr></code>: Works on all x86 CPUs and should
have reasonable performance. The default jump threshold is 8. This is the
default.
<li><code><nobr>nop</nobr></code>: Pad out with
<code><nobr>NOP</nobr></code> instructions. The only difference compared to
the standard <code><nobr>ALIGN</nobr></code> macro is that NASM can still
jump over a large padding area. The default jump threshold is 16.
<li><code><nobr>k7</nobr></code>: Optimize for the AMD K7 (Athlon/Althon
XP). These instructions should still work on all x86 CPUs. The default jump
threshold is 16.
<li><code><nobr>k8</nobr></code>: Optimize for the AMD K8 (Opteron/Althon
64). These instructions should still work on all x86 CPUs. The default jump
threshold is 16.
<li><code><nobr>p6</nobr></code>: Optimize for Intel CPUs. This uses the
long <code><nobr>NOP</nobr></code> instructions first introduced in Pentium
Pro. This is incompatible with all CPUs of family 5 or lower, as well as
some VIA CPUs and several virtualization solutions. The default jump
threshold is 16.
</ul>
<p>The macro <code><nobr>__ALIGNMODE__</nobr></code> is defined to contain
the current alignment mode. A number of other macros beginning with
<code><nobr>__ALIGN_</nobr></code> are used internally by this macro
package.
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