From 56779034530944eb6171d843f652f3fba710ed30 Mon Sep 17 00:00:00 2001 From: Aurelien Jarno Date: Mon, 10 Jan 2011 18:30:05 +0100 Subject: tcg arm/mips/ia64: add a comment about retranslation and caches Add a comment about cache coherency and retranslation, so that people developping new targets based on existing ones are warned of the issue. Acked-by: Edgar E. Iglesias Signed-off-by: Aurelien Jarno --- tcg/mips/tcg-target.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) (limited to 'tcg/mips') diff --git a/tcg/mips/tcg-target.c b/tcg/mips/tcg-target.c index 4e92a50e6f..e04b0dc32f 100644 --- a/tcg/mips/tcg-target.c +++ b/tcg/mips/tcg-target.c @@ -351,7 +351,9 @@ static inline void tcg_out_opc_imm(TCGContext *s, int opc, int rt, int rs, int i */ static inline void tcg_out_opc_br(TCGContext *s, int opc, int rt, int rs) { - /* We need to keep the offset unchanged for retranslation */ + /* We pay attention here to not modify the branch target by reading + the existing value and using it again. This ensure that caches and + memory are kept coherent during retranslation. */ uint16_t offset = (uint16_t)(*(uint32_t *) s->code_ptr); tcg_out_opc_imm(s, opc, rt, rs, offset); -- cgit v1.2.3