From 9ee6e8bb853bdea7ef6c645a1a07aa55fd206aba Mon Sep 17 00:00:00 2001 From: pbrook Date: Sun, 11 Nov 2007 00:04:49 +0000 Subject: ARMv7 support. git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3572 c046a42c-6fe2-441c-8c8c-71466251a162 --- cpu-exec.c | 13 ++++++++++++- 1 file changed, 12 insertions(+), 1 deletion(-) (limited to 'cpu-exec.c') diff --git a/cpu-exec.c b/cpu-exec.c index 4ba63fba31..aa58cbb24a 100644 --- a/cpu-exec.c +++ b/cpu-exec.c @@ -173,6 +173,7 @@ static inline TranslationBlock *tb_find_fast(void) flags |= (1 << 6); if (env->vfp.xregs[ARM_VFP_FPEXC] & (1 << 30)) flags |= (1 << 7); + flags |= (env->condexec_bits << 8); cs_base = 0; pc = env->regs[15]; #elif defined(TARGET_SPARC) @@ -511,8 +512,18 @@ int cpu_exec(CPUState *env1) env->exception_index = EXCP_FIQ; do_interrupt(env); } + /* ARMv7-M interrupt return works by loading a magic value + into the PC. On real hardware the load causes the + return to occur. The qemu implementation performs the + jump normally, then does the exception return when the + CPU tries to execute code at the magic address. + This will cause the magic PC value to be pushed to + the stack if an interrupt occured at the wrong time. + We avoid this by disabling interrupts when + pc contains a magic address. */ if (interrupt_request & CPU_INTERRUPT_HARD - && !(env->uncached_cpsr & CPSR_I)) { + && ((IS_M(env) && env->regs[15] < 0xfffffff0) + || !(env->uncached_cpsr & CPSR_I))) { env->exception_index = EXCP_IRQ; do_interrupt(env); } -- cgit v1.2.3