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path: root/tcg/sparc/tcg-target.h
AgeCommit message (Expand)AuthorFilesLines
2015-08-24tcg: Split trunc_shr_i32 opcode into extr[lh]_i64_i32Richard Henderson1-1/+2
2015-08-24tcg: rename trunc_shr_i32 into trunc_shr_i64_i32Aurelien Jarno1-1/+1
2015-06-03tcg: add TCG_TARGET_TLB_DISPLACEMENT_BITSPaolo Bonzini1-0/+1
2014-09-29tcg-sparc: Use UMULXHI instructionRichard Henderson1-1/+1
2014-09-29tcg-sparc: Use ADDXC in addsub2_i64Richard Henderson1-0/+6
2014-09-29tcg-sparc: Support addsub2_i64Richard Henderson1-2/+2
2014-06-04tcg: Remove TCG_TARGET_HAS_new_ldstRichard Henderson1-2/+0
2014-05-12tcg-sparc: Define TCG_TARGET_INSN_UNIT_SIZERichard Henderson1-0/+1
2014-04-28tcg-sparc: Implement muls2_i32Richard Henderson1-1/+1
2014-04-28tcg-sparc: Use 64-bit registers with sparcv8plusRichard Henderson1-11/+3
2014-04-28tcg-sparc: Support trunc_shr_i32Richard Henderson1-1/+1
2014-04-28tcg: Add INDEX_op_trunc_shr_i32Richard Henderson1-0/+1
2014-04-18tcg: Use HOST_WORDS_BIGENDIANRichard Henderson1-2/+0
2014-03-17tcg-sparc: Convert to new ldst opcodesRichard Henderson1-1/+1
2014-03-17tcg-sparc: Don't handle remainderRichard Henderson1-2/+2
2013-10-10tcg: Add qemu_ld_st_i32/64Richard Henderson1-0/+2
2013-09-20tcg-sparc: Fix parenthesis warningRichard Henderson1-1/+1
2013-09-02tcg: Allow TCG_TARGET_REG_BITS to be specified independantlyRichard Henderson1-0/+8
2013-09-02tcg: Change flush_icache_range arguments to uintptr_tRichard Henderson1-8/+4
2013-09-02tcg: Add muluh and mulsh opcodesRichard Henderson1-0/+4
2013-07-09tcg: Split rem requirement from div requirementRichard Henderson1-0/+2
2013-02-23tcg: Add signed multiword multiplication operationsRichard Henderson1-0/+2
2013-02-23tcg: Add 64-bit multiword arithmetic operationsRichard Henderson1-0/+3
2013-02-23tcg-sparc: Always implement 32-bit multiword opsRichard Henderson1-4/+3
2013-02-23tcg: Make 32-bit multiword operations optional for 64-bit hostsRichard Henderson1-0/+4
2012-12-19janitor: add guards to headersPaolo Bonzini1-0/+3
2012-10-19Merge branch 'linux-user-for-upstream' of git://git.linaro.org/people/rikuvoi...Aurelien Jarno1-2/+0
2012-10-13tcg-sparc: Use Z constraint for %g0Richard Henderson1-2/+3
2012-10-13tcg-sparc: Implement movcond.Richard Henderson1-2/+2
2012-10-12tcg: Remove TCG_TARGET_HAS_GUEST_BASE definePeter Maydell1-2/+0
2012-09-21tcg-sparc: Clean up cruft stemming from attempts to use global registers.Richard Henderson1-11/+7
2012-09-21tcg-sparc: Change AREG0 in generated code to %i0.Richard Henderson1-7/+1
2012-09-21tcg-sparc: Support GUEST_BASE.Richard Henderson1-0/+2
2012-09-21tcg-sparc: Assume v9 cpu always, i.e. force v8plus in 32-bit mode.Richard Henderson1-3/+4
2012-09-21tcg: Introduce movcondRichard Henderson1-0/+2
2012-09-15Remove unused CONFIG_TCG_PASS_AREG0 and dead codeBlue Swirl1-1/+0
2012-03-03w64: Change data type of parameters for flush_icache_rangeStefan Weil1-1/+2
2011-11-14tcg: Standardize on TCGReg as the enum for hard registersRichard Henderson1-2/+2
2011-10-01tcg: Don't declare TCG_TARGET_REG_BITS in tcg-target.hStefan Weil1-6/+0
2011-08-21tcg: Always define all of the TCGOpcode enum members.Richard Henderson1-33/+35
2010-06-16tcg: Optionally sign-extend 32-bit arguments for 64-bit hosts.Richard Henderson1-0/+4
2010-03-26tcg: Allow target-specific implementation of NOR.Richard Henderson1-0/+2
2010-03-26tcg: Allow target-specific implementation of NAND.Richard Henderson1-0/+2
2010-03-26tcg: Allow target-specific implementation of EQV.Richard Henderson1-0/+2
2010-03-26remove remaining occurrences AREG[1-9] and TCG_AREG[1-9]Paolo Bonzini1-7/+1
2010-02-20tcg: Add comments for all optional instructions not implemented.Richard Henderson1-6/+16
2010-02-20tcg-sparc: Implement ORC.Richard Henderson1-0/+2
2010-02-20tcg-sparc: Implement ANDC.Richard Henderson1-0/+2
2010-02-20tcg-sparc: Implement not.Richard Henderson1-0/+2
2010-02-20tcg-sparc: Implement neg.Richard Henderson1-2/+3
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