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2012-09-26tcg/mips: fix MIPS32(R2) detectionAurelien Jarno2-9/+9
2012-09-22Revert "tcg/mips"Aurelien Jarno1-2/+2
2012-09-22tcg/mipsAurelien Jarno1-2/+2
2012-09-22tcg: Remove tcg_target_get_call_iarg_regs_countStefan Weil1-6/+0
2012-09-22tcg/mips: implement movcond op on MIPS32R2Aurelien Jarno2-0/+77
2012-09-22tcg/mips: implement deposit op on MIPS32R2Aurelien Jarno2-1/+10
2012-09-22tcg/mips: implement rotl/rotr ops on MIPS32R2Aurelien Jarno2-1/+22
2012-09-22tcg/mips: optimize bswap{16,16s,32} on MIPS32R2Aurelien Jarno2-7/+38
2012-09-22tcg/mips: optimize brcond arg, 0Aurelien Jarno1-8/+30
2012-09-22tcg/mips: use stack for TCG tempsAurelien Jarno1-4/+6
2012-09-22tcg/mips: don't use global pointerAurelien Jarno1-1/+1
2012-09-22tcg/mips: use TCGArg or TCGReg instead of intAurelien Jarno1-28/+35
2012-09-22tcg/mips: kill warnings in user modeAurelien Jarno1-41/+43
2012-09-22tcg-mips: fix wrong usage of 'Z' constraintAurelien Jarno1-8/+8
2012-09-21tcg: Introduce movcondRichard Henderson1-0/+1
2012-09-15Remove unused CONFIG_TCG_PASS_AREG0 and dead codeBlue Swirl2-29/+3
2012-08-28tcg/mips: fix broken CONFIG_TCG_PASS_AREG0 codeAurelien Jarno1-59/+99
2012-03-18softmmu templates: optionally pass CPUState to memory access functionsBlue Swirl1-0/+44
2012-03-14Rename CPUState -> CPUArchStateAndreas Färber1-7/+7
2012-03-03w64: Change data type of parameters for flush_icache_rangeStefan Weil1-1/+2
2011-11-14tcg: Use TCGReg for standard tcg-target entry points.Richard Henderson1-6/+7
2011-11-14tcg: Standardize on TCGReg as the enum for hard registersRichard Henderson1-2/+2
2011-10-01tcg: Don't declare TCG_TARGET_REG_BITS in tcg-target.hStefan Weil1-1/+0
2011-08-21tcg: Always define all of the TCGOpcode enum members.Richard Henderson1-15/+16
2011-07-20tcg/mips: Fix regression caused by typo (copy + paste bug)Stefan Weil1-1/+1
2011-06-26Delegate setup of TCG temporaries to targetsBlue Swirl1-0/+2
2011-06-26cpu-exec.c: avoid AREG0 useBlue Swirl1-5/+3
2011-06-03Use the correct header in the TCG MIPS code to find cacheflush() on OpenBSD.Brad1-0/+4
2011-01-12tcg arm/mips/ia64: add a comment about retranslation and cachesAurelien Jarno1-1/+3
2011-01-08tcg/mips: fix branch target change during code retranslationAurelien Jarno1-1/+1
2010-06-09tcg: Make some tcg-target.c routines static.Richard Henderson1-2/+2
2010-06-09tcg: Add TYPE parameter to tcg_out_mov.Richard Henderson1-14/+14
2010-04-14tcp/mips: Change TCG_AREG0 (fp -> s0)Stefan Weil2-3/+4
2010-04-05tcg/mips: use seb/seh instructions on MIPS32R2Aurelien Jarno2-8/+41
2010-04-05tcg/mips: fix 64-bit linux-user on big endian MIPSAurelien Jarno1-4/+4
2010-04-05Split TLB addend and target_phys_addr_tPaul Brook1-2/+2
2010-03-29tcg/mips: fix branch offset during retranslationAurelien Jarno1-19/+30
2010-03-27tcg-mips: add guest base supportAurelien Jarno2-29/+39
2010-03-27tcg/mips: implement the not_i32 op the same way as gccAurelien Jarno1-1/+1
2010-03-27tcg-mips: implement norAurelien Jarno2-1/+5
2010-03-26tcg: Disambiguate qemu_ld32u with 32-bit and 64-bit outputs.Richard Henderson1-3/+3
2010-03-26tcg: Allow target-specific implementation of NOR.Richard Henderson1-0/+1
2010-03-26tcg: Allow target-specific implementation of NAND.Richard Henderson1-0/+1
2010-03-26tcg: Allow target-specific implementation of EQV.Richard Henderson1-0/+1
2010-03-26tcg: Use TCGCond where appropriate.Richard Henderson1-4/+4
2010-03-26tcg: Name the opcode enumeration.Richard Henderson1-1/+1
2010-03-26remove remaining occurrences AREG[1-9] and TCG_AREG[1-9]Paolo Bonzini1-2/+0
2010-02-20tcg: Add comments for all optional instructions not implemented.Richard Henderson1-1/+3
2010-02-09tcg/mips: fix crash in tcg_out_qemu_ld()Aurelien Jarno1-2/+2
2010-02-09tcg/mips: implement setcond2Aurelien Jarno1-12/+80
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