summaryrefslogtreecommitdiff
path: root/tcg/arm
AgeCommit message (Collapse)AuthorFilesLines
2013-10-12tcg-arm: Improve GUEST_BASE qemu_ld/stRichard Henderson1-104/+116
If we pull the code to emit the actual load/store into a subroutine, we can share the reg+reg addressing mode code between softmmu and usermode. This lets us load GUEST_BASE into a temporary register rather than attempting to add it piece-wise to the address. Which lets us use movw+movt for armv7, rather than (up to) 4 adds. Code size for pre-armv7 stays the same. Signed-off-by: Richard Henderson <rth@twiddle.net>
2013-10-12tcg-arm: Convert to new ldst opcodesRichard Henderson2-71/+38
Signed-off-by: Richard Henderson <rth@twiddle.net>
2013-10-12tcg-arm: Tidy variable naming convention in qemu_ld/stRichard Henderson1-115/+115
s/addr_reg2/addrhi/ s/addr_reg/addrlo/ s/data_reg2/datahi/ s/data_reg/datalo/ Signed-off-by: Richard Henderson <rth@twiddle.net>
2013-10-12tcg-arm: Convert to le/be ldst helpersRichard Henderson1-21/+29
Signed-off-by: Richard Henderson <rth@twiddle.net>
2013-10-12tcg-arm: Use TCGMemOp within qemu_ldst routinesRichard Henderson1-64/+61
Signed-off-by: Richard Henderson <rth@twiddle.net>
2013-10-10tcg: Add qemu_ld_st_i32/64Richard Henderson1-0/+2
Step two in the transition, adding the new ldst opcodes. Keep the old opcodes around until all backends support the new opcodes. Signed-off-by: Richard Henderson <rth@twiddle.net>
2013-10-10tcg: Add tcg-be-ldst.hRichard Henderson1-24/+3
Move TCGLabelQemuLdst and related stuff out of tcg.h. Signed-off-by: Richard Henderson <rth@twiddle.net>
2013-10-01tcg-arm: Move the tlb addend load earlierRichard Henderson1-5/+6
There are free scheduling slots between the sequence of comparison instructions. This requires changing the register in use to avoid conflict with those compares. Signed-off-by: Richard Henderson <rth@twiddle.net>
2013-10-01tcg-arm: Remove restriction on qemu_ld output registerRichard Henderson1-24/+34
The main intent of the patch is to allow the tlb addend register to be changed, without tying that change to the constraint. But the most common side-effect seems to be to enable usage of ldrd with the r0,r1 pair. Signed-off-by: Richard Henderson <rth@twiddle.net>
2013-10-01tcg-arm: Return register containing tlb addendRichard Henderson1-29/+30
Preparatory to rescheduling the tlb load, and changing said register. Continues to use R1 for now. Signed-off-by: Richard Henderson <rth@twiddle.net>
2013-10-01tcg-arm: Move load of tlb addend into tcg_out_tlb_readRichard Henderson1-37/+23
This allows us to make more intelligent decisions about the relative offsets of the tlb comparator and the addend, avoiding any need of writeback addressing. Signed-off-by: Richard Henderson <rth@twiddle.net>
2013-10-01tcg-arm: Use QEMU_BUILD_BUG_ON to verify constraints on tlbRichard Henderson1-5/+10
One of the two constraints we already checked via #if, but the tlb offset distance was only checked at runtime. Signed-off-by: Richard Henderson <rth@twiddle.net>
2013-10-01tcg-arm: Use strd for tcg_out_arg_reg64Richard Henderson1-3/+10
Signed-off-by: Richard Henderson <rth@twiddle.net>
2013-10-01tcg-arm: Rearrange slow-path qemu_ld/stRichard Henderson1-90/+87
Use the new helper_ret_*_mmu routines. Use a conditional call to arrange for a tail-call from the store path, and to load the return address for the helper for the load path. Signed-off-by: Richard Henderson <rth@twiddle.net>
2013-10-01tcg-arm: Use ldrd/strd for appropriate qemu_ld/st64Richard Henderson1-5/+43
Reviewed-by: Aurelien Jarno <aurelien@aurel32.net> Signed-off-by: Richard Henderson <rth@twiddle.net>
2013-09-02exec: Split softmmu_defs.hRichard Henderson1-2/+0
The _cmmu helpers can be moved to exec-all.h. The helpers that are used from TCG will shortly need access to tcg_target_long so move their declarations into tcg.h. This requires minor include adjustments to all TCG backends. Reviewed-by: Aurelien Jarno <aurelien@aurel32.net> Signed-off-by: Richard Henderson <rth@twiddle.net>
2013-09-02tcg: Change tcg_out_ld/st offset to intptr_tRichard Henderson1-2/+2
Reviewed-by: Aurelien Jarno <aurelien@aurel32.net> Signed-off-by: Richard Henderson <rth@twiddle.net>
2013-09-02tcg: Change relocation offsets to intptr_tRichard Henderson1-4/+4
Reviewed-by: Aurelien Jarno <aurelien@aurel32.net> Signed-off-by: Richard Henderson <rth@twiddle.net>
2013-09-02tcg: Change flush_icache_range arguments to uintptr_tRichard Henderson1-5/+4
Reviewed-by: Aurelien Jarno <aurelien@aurel32.net> Signed-off-by: Richard Henderson <rth@twiddle.net>
2013-09-02tcg: Add muluh and mulsh opcodesRichard Henderson1-0/+2
Use them in places where mulu2 and muls2 are used. Optimize mulx2 with dead low part to mulxh. Reviewed-by: Aurelien Jarno <aurelien@aurel32.net> Signed-off-by: Richard Henderson <rth@twiddle.net>
2013-07-09tcg-arm: Implement tcg_register_jitRichard Henderson1-9/+67
Allows unwinding past the code_gen_buffer. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <rth@twiddle.net>
2013-07-09tcg-arm: Use AT_PLATFORM to detect the host ISARichard Henderson1-4/+16
With this we can generate armv7 insns even when the OS compiles for a lower common denominator. The macros are arranged so that when we do compile for a given ISA, all of the runtime checks for that ISA are optimized away. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <rth@twiddle.net>
2013-07-09tcg-arm: Simplify logic in detecting the ARM ISA in useRichard Henderson1-39/+23
GCC 4.8 defines a handy __ARM_ARCH symbol that we can use, which will make us nicely forward compatible with ARMv8 AArch32. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <rth@twiddle.net>
2013-07-09tcg-arm: Rename use_armv5_instructions to use_armvt5_instructionsRichard Henderson1-6/+6
As it really controls the availability of a thumb interworking instruction on armv5t. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <rth@twiddle.net>
2013-07-09tcg-arm: Make use of conditional availability of opcodes for divideRichard Henderson2-8/+22
We can now detect and use divide instructions at runtime, rather than having to restrict their availability to compile-time. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <rth@twiddle.net>
2013-07-09tcg-arm: Don't implement remRichard Henderson2-16/+1
Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <rth@twiddle.net>
2013-07-09tcg: Split rem requirement from div requirementRichard Henderson1-0/+2
There are several hosts with only a "div" insn. Remainder is computed manually from the quotient and inputs. We can do this generically. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <rth@twiddle.net>
2013-06-05tcg: Remove redundant tcg_target_init checksRichard Henderson1-6/+0
We've got a compile-time check for the condition in exec/cpu-defs.h. Reviewed-by: Andreas Färber <afaerber@suse.de> Reviewed-by: liguang <lig.fnst@cn.fujitsu.com> Signed-off-by: Richard Henderson <rth@twiddle.net>
2013-05-03tcg-arm: Use movi32 in exit_tbRichard Henderson1-9/+7
Avoid the mini constant pool for armv7, and avoid replicating the test for pre-v7. Signed-off-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2013-05-03tcg-arm: Fix 64-bit tlb load for pre-v6Richard Henderson1-1/+1
Found by inspection, since the effect of the bug was simply to send all memory ops through the slow path. Signed-off-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2013-04-27tcg-arm: Remove long jump from tcg_out_goto_labelRichard Henderson1-6/+1
Branches within a TB will always be within 16MB. Signed-off-by: Richard Henderson <rth@twiddle.net>
2013-04-27tcg-arm: Convert to CONFIG_QEMU_LDST_OPTIMIZATIONRichard Henderson1-107/+202
Move the slow path out of line, as the TODO's mention. This allows the fast path to be unconditional, which can speed up the fast path as well, depending on the core. Signed-off-by: Richard Henderson <rth@twiddle.net>
2013-04-27tcg-arm: Use movi32 + blx for calls on v7Richard Henderson1-0/+3
Work better with branch predition when we have movw+movt, as the size of the code is the same. Perhaps re-evaluate when we have a proper constant pool. Reviewed-by: Aurelien Jarno <aurelien@aurel32.net> Signed-off-by: Richard Henderson <rth@twiddle.net>
2013-04-27tcg-arm: Delete the 'S' constraintRichard Henderson1-4/+2
After the previous patch, 's' and 'S' are the same. Signed-off-by: Richard Henderson <rth@twiddle.net>
2013-04-27tcg-arm: Improve scheduling of tcg_out_tlb_readRichard Henderson1-53/+57
The schedule was fully serial, with no possibility for dual issue. The old schedule had a minimal issue of 7 cycles; the new schedule has a minimal issue of 5 cycles. Signed-off-by: Richard Henderson <rth@twiddle.net>
2013-04-27tcg-arm: Split out tcg_out_tlb_readRichard Henderson1-99/+70
Share code between qemu_ld and qemu_st to process the tlb. Reviewed-by: Aurelien Jarno <aurelien@aurel32.net> Signed-off-by: Richard Henderson <rth@twiddle.net>
2013-04-27tcg-arm: Cleanup most primitive load store subroutinesRichard Henderson1-124/+111
Use even more primitive helper functions to avoid lots of duplicated code. Reviewed-by: Aurelien Jarno <aurelien@aurel32.net> Signed-off-by: Richard Henderson <rth@twiddle.net>
2013-04-27tcg-arm: Cleanup multiply subroutinesRichard Henderson1-40/+45
Make the code more readable by only having one copy of the magic numbers, swapping registers as needed prior to that. Speed the compiler by not applying the rd == rn avoidance for v6 or later. Reviewed-by: Aurelien Jarno <aurelien@aurel32.net> Signed-off-by: Richard Henderson <rth@twiddle.net>
2013-04-27tcg-arm: Use R12 for the tcg temporaryRichard Henderson1-1/+1
R12 is call clobbered, while R8 is call saved. This change gives tcg one more call saved register for real data. Reviewed-by: Aurelien Jarno <aurelien@aurel32.net> Signed-off-by: Richard Henderson <rth@twiddle.net>
2013-04-27tcg-arm: Use TCG_REG_TMP name for the tcg temporaryRichard Henderson1-58/+60
Don't hard-code R8. Reviewed-by: Aurelien Jarno <aurelien@aurel32.net> Signed-off-by: Richard Henderson <rth@twiddle.net>
2013-04-27tcg-arm: Implement division instructionsRichard Henderson2-1/+42
An armv7 extension implements division, present on Cortex A15. Reviewed-by: Aurelien Jarno <aurelien@aurel32.net> Signed-off-by: Richard Henderson <rth@twiddle.net>
2013-04-27tcg-arm: Implement deposit for armv7Richard Henderson2-4/+42
We have BFI and BFC available for implementing it. Signed-off-by: Richard Henderson <rth@twiddle.net>
2013-04-27tcg-arm: Improve constant generationRichard Henderson1-23/+44
Try fully rotated arguments to mov and mvn before trying movt or full decomposition. Begin decomposition with mvn when it looks like it'll help. Examples include -: mov r9, #0x00000fa0 -: orr r9, r9, #0x000ee000 -: orr r9, r9, #0x0ff00000 -: orr r9, r9, #0xf0000000 +: mvn r9, #0x0000005f +: eor r9, r9, #0x00011000 Reviewed-by: Aurelien Jarno <aurelien@aurel32.net> Signed-off-by: Richard Henderson <rth@twiddle.net>
2013-04-27tcg-arm: Handle constant arguments to add2/sub2Richard Henderson1-48/+58
We get to re-use the _rIN and _rIK subroutines to handle the various combinations of add vs sub. Fold the << 21 into the opcode enum values so that we can explicitly add TO_CPSR as desired. Reviewed-by: Aurelien Jarno <aurelien@aurel32.net> Signed-off-by: Richard Henderson <rth@twiddle.net>
2013-04-27tcg-arm: Use tcg_out_dat_rIN for comparesRichard Henderson1-20/+20
This allows us to emit CMN instructions. Reviewed-by: Aurelien Jarno <aurelien@aurel32.net> Signed-off-by: Richard Henderson <rth@twiddle.net>
2013-04-27tcg-arm: Allow constant first argument to subRichard Henderson1-3/+12
This allows the generation of RSB instructions. Reviewed-by: Aurelien Jarno <aurelien@aurel32.net> Signed-off-by: Richard Henderson <rth@twiddle.net>
2013-04-27tcg-arm: Handle negated constant arguments to and/subRichard Henderson1-6/+35
This greatly improves code generation for addition of small negative constants. Reviewed-by: Aurelien Jarno <aurelien@aurel32.net> Signed-off-by: Richard Henderson <rth@twiddle.net>
2013-04-27tcg-arm: Use bic to implement and with constantRichard Henderson2-14/+44
This greatly improves the code we can produce for deposit without armv7 support. Reviewed-by: Aurelien Jarno <aurelien@aurel32.net> Signed-off-by: Richard Henderson <rth@twiddle.net>
2013-04-27tcg-arm: Fix local stack frameRichard Henderson1-74/+47
We were not allocating TCG_STATIC_CALL_ARGS_SIZE, so this meant that any helper with more than 4 arguments would clobber the saved regs. Realizing that we're supposed to have this memory pre-allocated means we can clean up the tcg_out_arg functions, which were trying to do more stack allocation. Allocate stack memory for the TCG temporaries while we're at it. Signed-off-by: Richard Henderson <rth@twiddle.net>
2013-02-23tcg-arm: Implement muls2_i32Richard Henderson2-1/+5
We even had the encoding of smull already handy... Cc: Andrzej Zaborowski <balrogg@gmail.com> Signed-off-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-23 04:40:29 +0000