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2012-10-19Merge branch 'linux-user-for-upstream' of ↵Aurelien Jarno1-2/+0
git://git.linaro.org/people/rikuvoipio/qemu * 'linux-user-for-upstream' of git://git.linaro.org/people/rikuvoipio/qemu: linux-user: register align p{read, write}64 linux-user: ppc: mark as long long aligned tcg: Remove TCG_TARGET_HAS_GUEST_BASE define configure: Remove unnecessary host_guest_base code linux-user: If loading fails, print error as string, not number linux-user: Fix siginfo handling alpha-linux-user: Fix sigaltstack structure definition linux-user: Implement gethostname linux-user: Perform more checks on iovec lists linux-user: fix multi-threaded /proc/self/maps linux-user: fix statfs
2012-10-17tcg/arm: Implement movcond_i32Peter Maydell2-1/+11
Implement movcond_i32 for ARM, as the sequence mov dst, v2 (implicitly done by the tcg common code) cmp c1, c2 movCC dst, v1 Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2012-10-17tcg/arm: Factor out code to emit immediate or reg-reg opPeter Maydell1-26/+20
The code to emit either an immediate cmp or a register cmp insn is duplicated in several places; factor it out into its own function. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2012-10-12tcg: Remove TCG_TARGET_HAS_GUEST_BASE definePeter Maydell1-2/+0
GUEST_BASE support is now supported by all TCG backends, and is now mandatory. Drop the now-pointless TCG_TARGET_HAS_GUEST_BASE define (set by every backend) and the error if it is unset. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Riku Voipio <riku.voipio@linaro.org>
2012-10-06Merge branch 'trivial-patches' of git://github.com/stefanha/qemuAurelien Jarno1-12/+3
* 'trivial-patches' of git://github.com/stefanha/qemu: versatilepb: Use symbolic indices for ARM PIC qdev: kill bogus comment qemu-barrier: Fix compiler version check for future gcc versions hw: Add missing 'static' attribute for QEMUMachine cleanup useless return sentence qemu-sockets: Fix compiler warning (regression for MinGW) vnc: Fix spelling (hellmen -> hellman) in comment slirp: Fix spelling in comment (enought -> enough, insure -> ensure) tcg/arm: Use tcg_out_mov_reg rather than inline equivalent code cpu: Add missing 'static' attribute to qemu_global_mutex configure: Support empty target list (--target-list=) hw: Fix return value check for bdrv_read, bdrv_write
2012-10-06tcg: Add TCG_COND_NEVER, TCG_COND_ALWAYSRichard Henderson1-1/+1
There are several cases that can be handled easier inside both translators and code generators if we have out-of-band values for conditions. It's easy enough to handle ALWAYS and NEVER in the natural way inside the tcg middle-end. Signed-off-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2012-10-06tcg: remove obsolete jmp opAurelien Jarno1-7/+0
The TCG jmp operation doesn't really make sense in the QEMU context, it is unused, it is not implemented by some targets, and it is wrongly implemented by some others. This patch simply removes it. Reviewed-by: Richard Henderson <rth@twiddle.net> Acked-by: Blue Swirl <blauwirbel@gmail.com> Acked-by: Stefan Weil<sw@weilnetz.de> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2012-10-05tcg/arm: Use tcg_out_mov_reg rather than inline equivalent codePeter Maydell1-12/+3
Use the recently introduced tcg_out_mov_reg() function rather than the equivalent inline code. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Aurelien Jarno <aurelien@aurel32.net> Signed-off-by: Stefan Hajnoczi <stefanha@gmail.com>
2012-09-22tcg: Remove tcg_target_get_call_iarg_regs_countStefan Weil1-6/+0
The TCG targets no longer need individual implementations. Since commit 6a18ae2d2947532d5c26439548afa0481c4529f9, 'flags' is no longer used in tcg_target_get_call_iarg_regs_count. The remaining tcg_target_get_call_iarg_regs_count is trivial and only called once. Therefore the patch eliminates it completely. Signed-off-by: Stefan Weil <sw@weilnetz.de> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2012-09-21tcg: Introduce movcondRichard Henderson1-0/+1
Implemented with setcond if the target does not provide the optional opcode. Signed-off-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2012-09-15Remove unused CONFIG_TCG_PASS_AREG0 and dead codeBlue Swirl2-29/+3
Now that CONFIG_TCG_PASS_AREG0 is enabled for all targets, remove dead code and support for !CONFIG_TCG_PASS_AREG0 case. Remove dyngen-exec.h and all references to it. Although included by hw/spapr_hcall.c, it does not seem to use it. Remove unused HELPER_CFLAGS. Signed-off-by: Blue Swirl <blauwirbel@gmail.com> Reviewed-by: Richard Henderson <rth@twiddle.net>
2012-08-26tcg/arm: Fix broken CONFIG_TCG_PASS_AREG0 codePeter Maydell1-93/+144
The CONFIG_TCG_PASS_AREG0 code for calling ld/st helpers was broken in that it did not respect the ABI requirement that 64 bit values were passed in even-odd register pairs. The simplest way to fix this is to implement some new utility functions for marshalling function arguments into the correct registers and stack, so that the code which sets up the address and data arguments does not need to care whether there has been a preceding env argument. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2012-03-18softmmu templates: optionally pass CPUState to memory access functionsBlue Swirl1-0/+53
Optionally, make memory access helpers take a parameter for CPUState instead of relying on global env. On most targets, perform simple moves to reorder registers. On i386, switch from regparm(3) calling convention to standard stack-based version. Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2012-03-14Rename CPUState -> CPUArchStateAndreas Färber1-11/+11
Scripted conversion: for file in *.[hc] hw/*.[hc] hw/kvm/*.[hc] linux-user/*.[hc] linux-user/m68k/*.[hc] bsd-user/*.[hc] darwin-user/*.[hc] tcg/*/*.[hc] target-*/cpu.h; do sed -i "s/CPUState/CPUArchState/g" $file done All occurrences of CPUArchState are expected to be replaced by QOM CPUState, once all targets are QOM'ified and common fields have been extracted. Signed-off-by: Andreas Färber <afaerber@suse.de> Reviewed-by: Anthony Liguori <aliguori@us.ibm.com>
2012-03-03w64: Change data type of parameters for flush_icache_rangeStefan Weil1-1/+2
The TCG targets i386 and tci needed a change of the function prototype for w64. This change is currently not needed for the other TCG targets, but it can be applied to avoid code differences. Cc: Blue Swirl <blauwirbel@gmail.com> Cc: Andrzej Zaborowski <balrogg@gmail.com> Cc: Richard Henderson <rth@twiddle.net> Cc: Aurelien Jarno <aurelien@aurel32.net> Cc: Alexander Graf <agraf@suse.de> Signed-off-by: Stefan Weil <sw@weilnetz.de> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2012-01-13tcg-arm: fix a typo in commentsAurelien Jarno1-1/+1
ARM still doesn't support 16GB buffers in 32-bit modes, replace the 16GB by 16MB in the comment. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net> Signed-off-by: Stefan Hajnoczi <stefanha@linux.vnet.ibm.com>
2012-01-10tcg/arm: Use r6 as TCG_AREG0 to avoid clash with Thumb framepointerPeter Maydell1-1/+1
On ARM, in Thumb mode r7 is used for the framepointer; this meant that we would fail to compile in debug mode because we were using r7 for TCG_AREG0. Shift to r6 instead to avoid this clash. (Bug reported as LP:870990.) Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Andrzej Zaborowski <andrew.zaborowski@intel.com>
2011-12-14tcg/arm: remove fixed map code buffer restrictionDr. David Alan Gilbert1-19/+12
On ARM, don't map the code buffer at a fixed location, and fix up the call/goto tcg routines to let it do long jumps. Mapping the code buffer at a fixed address could sometimes result in it being mapped over the top of the heap with pretty random results. Signed-off-by: Dr. David Alan Gilbert <david.gilbert@linaro.org> Signed-off-by: Andrzej Zaborowski <andrew.zaborowski@intel.com>
2011-11-14tcg: Use TCGReg for standard tcg-target entry points.Richard Henderson1-6/+7
Including tcg_out_ld, tcg_out_st, tcg_out_mov, tcg_out_movi. Signed-off-by: Richard Henderson <rth@twiddle.net> Reviewed-by: Andreas Färber <afaerber@suse.de> Reviewed-by: Stefan Weil <sw@weilnetz.de> Signed-off-by: Alexander Graf <agraf@suse.de>
2011-11-14tcg: Standardize on TCGReg as the enum for hard registersRichard Henderson1-2/+2
Most targets did not name the enum; tci used TCGRegister. Signed-off-by: Richard Henderson <rth@twiddle.net> Reviewed-by: Andreas Färber <afaerber@suse.de> Reviewed-by: Stefan Weil <sw@weilnetz.de> Signed-off-by: Alexander Graf <agraf@suse.de>
2011-10-01tcg/arm: Remove unused tcg_out_addi()Peter Maydell1-15/+0
Remove the unused function tcg_out_addi() from the ARM TCG backend; this fixes a compilation failure on ARM hosts with newer gcc. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2011-10-01tcg: Don't declare TCG_TARGET_REG_BITS in tcg-target.hStefan Weil1-1/+0
It is now declared for all tcg targets in tcg.h, so the tcg target specific declarations are redundant. Signed-off-by: Stefan Weil <weil@mail.berlios.de> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2011-08-21tcg: Always define all of the TCGOpcode enum members.Richard Henderson1-14/+16
By always defining these symbols, we can eliminate a lot of ifdefs. To allow this to be checked reliably, the semantics of the TCG_TARGET_HAS_* macros must be changed from def/undef to true/false. This allows even more ifdefs to be removed, converting them into C if statements. Signed-off-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2011-06-26Delegate setup of TCG temporaries to targetsBlue Swirl1-0/+2
Delegate TCG temp_buf setup to targets, so that they can use a stack frame later instead. Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2011-06-26cpu-exec.c: avoid AREG0 useBlue Swirl1-7/+10
Make functions take a parameter for CPUState instead of relying on global env. Pass CPUState pointer to TCG prologue, which moves it to AREG0. Thanks to Peter Maydell and Laurent Desnogues for the ARM prologue change. Revert the hacks to avoid AREG0 use on Sparc hosts. Move cpu_has_work() and cpu_pc_from_tb() from exec.h to cpu.h. Compile the file without HELPER_CFLAGS. Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2011-03-24tcg/arm: Support host code being compiled for ThumbPeter Maydell1-9/+26
Although the TCG generated code is always in ARM mode, it is possible that the host code was compiled by gcc in Thumb mode (this is often the default for Linux distributions targeting ARM v7 only). Handle this by using BLX imm when doing a call from ARM into Thumb mode. Since BLX imm is not a conditionalisable instruction, we make tcg_out_call() no longer take a condition code; we were only ever using it with COND_AL anyway. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Andrzej Zaborowski <andrew.zaborowski@intel.com>
2011-01-12tcg arm/mips/ia64: add a comment about retranslation and cachesAurelien Jarno1-0/+3
Add a comment about cache coherency and retranslation, so that people developping new targets based on existing ones are warned of the issue. Acked-by: Edgar E. Iglesias <edgar.iglesias@gmail.com> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2011-01-10tcg/arm: improve constant loadingAurelien Jarno1-18/+21
Improve constant loading in two ways: - On all ARM versions, it's possible to load 0xffffff00 = -0x100 using the mvn rd, #0. Fix the conditions. - On <= ARMv6 versions, where movw and movt are not available, load the constants using mov and orr with rotations depending on the constant to load. This is very useful for example to load constants where the low byte is 0. This reduce the generated code size by about 7%. Also fix the coding style at the same time. Cc: Andrzej Zaborowski <balrog@zabor.org> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2011-01-08tcg/arm: fix qemu_st64 for big endian targetsAurelien Jarno1-1/+1
Due to a typo, qemu_st64 doesn't properly byteswap the 32-bit low word of a 64 bit word before saving it. This patch fixes that. Acked-by: Andrzej Zaborowski <balrogg@gmail.com> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2011-01-08tcg/arm: fix branch target change during code retranslationAurelien Jarno1-8/+20
QEMU uses code retranslation to restore the CPU state when an exception happens. For it to work the retranslation must not modify the generated code. This is what is currently implemented in ARM TCG. However on CPU that don't have icache/dcache/memory synchronised like ARM, this requirement is stronger and code retranslation must not modify the generated code "atomically", as the cache line might be flushed at any moment (interrupt, exception, task switching), even if not triggered by QEMU. The probability for this to happen is very low, and depends on cache size and associativiy, machine load, interrupts, so the symptoms are might happen randomly. This requirement is currently not followed in tcg/arm, for the load/store code, which basically has the following structure: 1) tlb access code is written 2) conditional fast path code is written 3) branch is written with a temporary target 4) slow path code is written 5) branch target is updated The cache lines corresponding to the retranslated code is not flushed after code retranslation as the generated code is supposed to be the same. However if the cache line corresponding to the branch instruction is flushed between step 3 and 5, and is not flushed again before the code is executed again, the branch target is wrong. In the guest, the symptoms are MMU page fault at a random addresses, which leads to kernel page fault or segmentation faults. The patch fixes this issue by avoiding writing the branch target until it is known, that is by writing only the branch instruction first, and later only the offset. This fixes booting linux guests on ARM hosts (tested: arm, i386, mips, mipsel, sh4, sparc). Acked-by: Edgar E. Iglesias <edgar.iglesias@gmail.com> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2010-06-09tcg: Make some tcg-target.c routines static.Richard Henderson1-2/+2
Both tcg_target_init and tcg_target_qemu_prologue are unused outside of tcg.c. Signed-off-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2010-06-09tcg: Add TYPE parameter to tcg_out_mov.Richard Henderson1-1/+1
Mirror tcg_out_movi in having a TYPE parameter. This allows x86_64 to perform the move at the proper width, which may elide a REX prefix. Introduce a TCG_TYPE_REG enumerator to represent the "native width" of the host register, and to distinguish the usage from "pointer data" as represented by the existing TCG_TYPE_PTR. Update all targets to match. Signed-off-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2010-04-25tcg/arm: fix condition in zero/sign extension functionsAurelien Jarno1-6/+6
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2010-04-19tcg/arm: don't try to load constants using pcAurelien Jarno1-7/+0
There is statistically almost 0 chances to use this code, so remove it. Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2010-04-19tcg/arm: optimize register allocation orderAurelien Jarno1-5/+5
The beginning of the register allocation order list on the TCG arm target matches the list of clobbered registers. This means that when an helper is called, there is almost always clobbered registers that have to be spilled. Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2010-04-19tcg/arm: fix argument alignment in qemu_st64Aurelien Jarno1-9/+10
64-bit arguments should be aligned on an even register as specified by the "Procedure Call Standard for the ARM Architecture". Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2010-04-19tcg/arm: remove useless register tests in qemu_ld/stAurelien Jarno1-20/+10
addr_reg, data_reg and data_reg2 can't be register r0 or r1 du to the constraints. Don't check if they equals these registers. Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2010-04-19tcg/arm: bswap arguments in qemu_ld/st if neededAurelien Jarno1-69/+159
On big endian targets, data arguments of qemu_ld/st ops have to be byte swapped. Two temporary registers are needed for qemu_st to do the bswap. r0 and r1 are used in system mode, do the same in user mode, which implies reworking the constraints. Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2010-04-19tcg/arm: use ext* ops in qemu_ldAurelien Jarno1-18/+12
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2010-04-19tcg/arm: remove conditional argument for qemu_ld/stAurelien Jarno1-51/+49
While it make sense to pass a conditional argument to tcg_out_*() functions as the ARM architecture allows that, it doesn't make sense for qemu_ld/st functions. These functions use comparison instructions and conditional execution already, so it is not possible to use a second level of conditional execution. Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2010-04-19tcg/arm: add bswap opsAurelien Jarno2-2/+44
Add an bswap16 and bswap32 ops, either using the rev and rev16 instructions on ARMv6+ or shifts and logical operations on previous ARM versions. In both cases the result use less instructions than the pure TCG version. These ops are also needed by the qemu_ld/st functions. Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2010-04-19tcg/arm: add ext16u opAurelien Jarno2-20/+50
Add an ext16u op, either using the uxth instruction on ARMv6+ or two shifts on previous ARM versions. In both cases the result use the same number or less instructions than the pure TCG version. Also move all sign extension code to separate functions, so that they can be reused in other parts of the code. Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2010-04-19tcg/arm: add rotation opsAurelien Jarno2-1/+20
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2010-04-19tcg/arm: use the blx instruction when possibleAurelien Jarno1-4/+12
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2010-04-19tcg/arm: sxtb and sxth are available starting with ARMv6Aurelien Jarno1-2/+2
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2010-04-19tcg/arm: add variables to define the allowed instructions setAurelien Jarno1-39/+84
Use a set of variables to define the allowed ARM instructions, depending on the __ARM_ARCH_*__ GCC defines. Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2010-04-19tcg/arm: align 64-bit arguments in function callsAurelien Jarno1-0/+1
As specified by the "Procedure Call Standard for the ARM Architecture". Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2010-04-19tcg/arm: replace integer values by registers enumAurelien Jarno1-109/+124
The TCG ARM backends uses integer values to refer to both immediate values and register number. This makes the code difficult to read. The patch below replaces all (if I haven't miss any ;-) integer values representing register number by TCG_REG_* enum values. Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2010-04-19tcg/arm: remove store signed functionsAurelien Jarno1-62/+10
Store signed functions doesn't make sense, and are not used. Remove them. Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2010-04-19tcg/arm: explicitely list clobbered/reserved regsAurelien Jarno2-5/+11
Instead of writing very compact code, declare all registers that are clobbered or reserved one by one. This makes the code easier to read. Also declare all the 16 registers to TCG, and mark pc as reserved. Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
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