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AgeCommit message (Expand)AuthorFilesLines
2015-01-20exec.c: Drop TARGET_HAS_ICE define and checksPeter Maydell1-2/+0
2015-01-03gen-icount: check cflags instead of use_icount globalPaolo Bonzini1-1/+1
2014-12-17target-xtensa: don't generate dead codeMax Filippov1-279/+321
2014-12-17target-xtensa: record available window in TB flagsMax Filippov4-62/+42
2014-12-17target-xtensa: fix translation for opcodes crossing page boundaryMax Filippov1-4/+23
2014-11-10target-xtensa: add missing window check for entryMax Filippov2-0/+12
2014-11-03Merge remote-tracking branch 'remotes/xtensa/tags/20141103-xtensa' into stagingPeter Maydell3-12/+74
2014-11-03target-xtensa: fix build for cores w/o windowed registersMax Filippov1-12/+19
2014-11-03target-xtensa: add core importing scriptMax Filippov1-0/+53
2014-11-03target-xtensa: add definition for XTHAL_INTTYPE_PROFILINGMax Filippov2-0/+2
2014-11-02target-xtensa: mark XtensaConfig structs as unusedPeter Maydell3-3/+3
2014-10-06gdbstub: Allow target CPUs to specify watchpoint STOP_BEFORE_ACCESS flagPeter Maydell1-0/+1
2014-09-25target-xtensa: Use cpu_exec_interrupt qom hookRichard Henderson3-0/+12
2014-09-12cpu-exec: Make debug_excp_handler a QOM CPU methodPeter Maydell3-4/+5
2014-08-12trace: [tcg] Include TCG-tracing header on all targetsLluís Vilanova1-0/+3
2014-06-05softmmu: introduce cpu_ldst.hPaolo Bonzini2-1/+2
2014-06-05softmmu: commonize helper definitionsPaolo Bonzini1-14/+1
2014-06-05softmmu: move ALIGNED_ONLY to cpu.hPaolo Bonzini2-1/+1
2014-06-05softmmu: make do_unaligned_access a method of CPUPaolo Bonzini3-6/+7
2014-05-28tcg: Invert the inclusion of helper.hRichard Henderson4-9/+4
2014-05-26target-xtensa: fix cross-page jumps/calls at the end of TBMax Filippov1-2/+2
2014-03-13cputlb: Change tlb_set_page() argument to CPUStateAndreas Färber1-4/+4
2014-03-13cputlb: Change tlb_flush() argument to CPUStateAndreas Färber1-1/+3
2014-03-13cputlb: Change tlb_flush_page() argument to CPUStateAndreas Färber1-4/+6
2014-03-13cpu-exec: Change cpu_resume_from_signal() argument to CPUStateAndreas Färber1-1/+1
2014-03-13exec: Change cpu_watchpoint_{insert,remove{,_by_ref,_all}} argumentAndreas Färber1-3/+6
2014-03-13translate-all: Change cpu_restore_state() argument to CPUStateAndreas Färber1-2/+4
2014-03-13cpu-exec: Change cpu_loop_exit() argument to CPUStateAndreas Färber1-2/+2
2014-03-13exec: Change tlb_fill() argument to CPUStateAndreas Färber1-2/+4
2014-03-13cpu: Move breakpoints field from CPU_COMMON to CPUStateAndreas Färber1-2/+3
2014-03-13cpu: Move watchpoint fields from CPU_COMMON to CPUStateAndreas Färber2-4/+6
2014-03-13cpu: Move exception_index field from CPU_COMMON to CPUStateAndreas Färber2-10/+14
2014-03-13cpu: Turn cpu_has_work() into a CPUClass hookAndreas Färber2-7/+8
2014-03-13target-xtensa: Clean up ENV_GET_CPU() usageAndreas Färber2-2/+4
2014-02-24target-xtensa: provide HW confg ID registersMax Filippov4-3/+21
2014-02-24target-xtensa: refactor standard core configurationMax Filippov4-21/+13
2014-02-24target-xtensa: add basic checks to icache opcodesMax Filippov3-0/+33
2014-02-24target-xtensa: add basic checks to dcache opcodesMax Filippov1-0/+38
2014-02-24target-xtensa: add RRRI4 opcode format fieldsMax Filippov1-0/+9
2014-02-11exec: Make ldl_*_phys input an AddressSpaceEdgar E. Iglesias1-1/+2
2014-02-11exec: Make tb_invalidate_phys_addr input an ASEdgar E. Iglesias1-1/+2
2013-11-08target-xtensa: add missing DEBUG section to dc233c configMax Filippov1-0/+1
2013-10-15target-xtensa: add in_asm loggingMax Filippov1-0/+8
2013-10-10tcg: Move helper registration into tcg_context_initRichard Henderson1-2/+0
2013-09-02target: Include softmmu_exec.h where forgottenRichard Henderson1-0/+1
2013-09-02tcg: Change tcg_gen_exit_tb argument to uintptr_tRichard Henderson1-1/+1
2013-08-22aio / timers: Switch entire codebase to the new timer APIAlex Bligh1-1/+1
2013-08-05Merge remote-tracking branch 'filippov/tags/20130729-xtensa' into stagingAnthony Liguori3-23/+53
2013-07-29target-xtensa: check register window inlineMax Filippov1-8/+25
2013-07-29target-xtensa: don't generate dead code to access invalid SRsMax Filippov1-13/+18
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