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2015-12-17tricore: avoid "naked" qemu_logPaolo Bonzini1-2/+2
Cc: Bastian Koppelmann <kbastian@mail.uni-paderborn.de> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2015-10-09qdev: Protect device-list-properties against broken devicesMarkus Armbruster1-0/+6
Several devices don't survive object_unref(object_new(T)): they crash or hang during cleanup, or they leave dangling pointers behind. This breaks at least device-list-properties, because qmp_device_list_properties() needs to create a device to find its properties. Broken in commit f4eb32b "qmp: show QOM properties in device-list-properties", v2.1. Example reproducer: $ qemu-system-aarch64 -nodefaults -display none -machine none -S -qmp stdio {"QMP": {"version": {"qemu": {"micro": 50, "minor": 4, "major": 2}, "package": ""}, "capabilities": []}} { "execute": "qmp_capabilities" } {"return": {}} { "execute": "device-list-properties", "arguments": { "typename": "pxa2xx-pcmcia" } } qemu-system-aarch64: /home/armbru/work/qemu/memory.c:1307: memory_region_finalize: Assertion `((&mr->subregions)->tqh_first == ((void *)0))' failed. Aborted (core dumped) [Exit 134 (SIGABRT)] Unfortunately, I can't fix the problems in these devices right now. Instead, add DeviceClass member cannot_destroy_with_object_finalize_yet to mark them: * Hang during cleanup (didn't debug, so I can't say why): "realview_pci", "versatile_pci". * Dangling pointer in cpus: most CPUs, plus "allwinner-a10", "digic", "fsl,imx25", "fsl,imx31", "xlnx,zynqmp", because they create such CPUs * Assert kvm_enabled(): "host-x86_64-cpu", host-i386-cpu", "host-powerpc64-cpu", "host-embedded-powerpc-cpu", "host-powerpc-cpu" (the powerpc ones can't currently reach the assertion, because the CPUs are only registered when KVM is enabled, but the assertion is arguably in the wrong place all the same) Make qmp_device_list_properties() fail cleanly when the device is so marked. This improves device-list-properties from "crashes, hangs or leaves dangling pointers behind" to "fails". Not a complete fix, just a better-than-nothing work-around. In the above reproducer, device-list-properties now fails with "Can't list properties of device 'pxa2xx-pcmcia'". This also protects -device FOO,help, which uses the same machinery since commit ef52358 "qdev-monitor: include QOM properties in -device FOO, help output", v2.2. Example reproducer: $ qemu-system-aarch64 -machine none -device pxa2xx-pcmcia,help Before: qemu-system-aarch64: .../memory.c:1307: memory_region_finalize: Assertion `((&mr->subregions)->tqh_first == ((void *)0))' failed. After: Can't list properties of device 'pxa2xx-pcmcia' Cc: "Andreas Färber" <afaerber@suse.de> Cc: "Edgar E. Iglesias" <edgar.iglesias@gmail.com> Cc: Alexander Graf <agraf@suse.de> Cc: Anthony Green <green@moxielogic.com> Cc: Aurelien Jarno <aurelien@aurel32.net> Cc: Bastian Koppelmann <kbastian@mail.uni-paderborn.de> Cc: Blue Swirl <blauwirbel@gmail.com> Cc: Eduardo Habkost <ehabkost@redhat.com> Cc: Guan Xuetao <gxt@mprc.pku.edu.cn> Cc: Jia Liu <proljc@gmail.com> Cc: Leon Alrae <leon.alrae@imgtec.com> Cc: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Cc: Max Filippov <jcmvbkbc@gmail.com> Cc: Michael Walle <michael@walle.cc> Cc: Paolo Bonzini <pbonzini@redhat.com> Cc: Peter Maydell <peter.maydell@linaro.org> Cc: Richard Henderson <rth@twiddle.net> Cc: qemu-ppc@nongnu.org Cc: qemu-stable@nongnu.org Signed-off-by: Markus Armbruster <armbru@redhat.com> Reviewed-by: Eduardo Habkost <ehabkost@redhat.com> Message-Id: <1443689999-12182-10-git-send-email-armbru@redhat.com>
2015-10-07tcg: Remove gen_intermediate_code_pcRichard Henderson1-26/+5
It is no longer used, so tidy up everything reached by it. This includes the gen_opc_* arrays, the search_pc parameter and the inline gen_intermediate_code_internal functions. Reviewed-by: Aurelien Jarno <aurelien@aurel32.net> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <rth@twiddle.net>
2015-10-07tcg: Pass data argument to restore_state_to_opcRichard Henderson1-2/+3
The gen_opc_* arrays are already redundant with the data stored in the insn_start arguments. Transition restore_state_to_opc to use data from the latter. Reviewed-by: Aurelien Jarno <aurelien@aurel32.net> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <rth@twiddle.net>
2015-10-07tcg: Add TCG_MAX_INSNSRichard Henderson1-7/+13
Adjust all translators to respect it. Reviewed-by: Aurelien Jarno <aurelien@aurel32.net> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <rth@twiddle.net>
2015-10-07target-*: Increment num_insns immediately after tcg_gen_insn_startRichard Henderson1-2/+1
This does tidy the icount test common to all targets. Reviewed-by: Aurelien Jarno <aurelien@aurel32.net> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <rth@twiddle.net>
2015-10-07target-*: Unconditionally emit tcg_gen_insn_startRichard Henderson1-0/+2
While we're at it, emit the opcode adjacent to where we currently record data for search_pc. This puts gen_io_start et al on the "correct" side of the marker. Reviewed-by: Aurelien Jarno <aurelien@aurel32.net> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <rth@twiddle.net>
2015-09-25tricore: Remove ELF_MACHINE from cpu.hPeter Crosthwaite1-2/+0
The bootloader can just pass EM_TRICORE directly, as that is architecture specific code. This removes another architecture specific definition from the global namespace. Cc: Bastian Koppelmann <kbastian@mail.uni-paderborn.de> Acked-By: Bastian Koppelmann <kbastian@mail.uni-paderborn.de> Reviewed-by: Richard Henderson <rth@twiddle.net> Acked-By: Riku Voipio <riku.voipio@linaro.org> Signed-off-by: Peter Crosthwaite <crosthwaite.peter@gmail.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2015-09-11tlb: Add "ifetch" argument to cpu_mmu_index()Benjamin Herrenschmidt2-2/+2
This is set to true when the index is for an instruction fetch translation. The core get_page_addr_code() sets it, as do the SOFTMMU_CODE_ACCESS acessors. All targets ignore it for now, and all other callers pass "false". This will allow targets who wish to split the mmu index between instruction and data accesses to do so. A subsequent patch will do just that for PowerPC. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Message-Id: <1439796853-4410-2-git-send-email-benh@kernel.crashing.org> Signed-off-by: Richard Henderson <rth@twiddle.net>
2015-09-11maint: remove unused include for signal.hDaniel P. Berrange1-1/+0
A number of files were including signal.h but not using any of the functions it provides Signed-off-by: Daniel P. Berrange <berrange@redhat.com> Reviewed-by: Markus Armbruster <armbru@redhat.com> Signed-off-by: Michael Tokarev <mjt@tls.msk.ru>
2015-08-24tcg: Remove tcg_gen_trunc_i64_i32Richard Henderson1-10/+10
Replacing it with tcg_gen_extrl_i64_i32. Signed-off-by: Richard Henderson <rth@twiddle.net>
2015-08-24tcg: Split trunc_shr_i32 opcode into extr[lh]_i64_i32Richard Henderson1-6/+6
Rather than allow arbitrary shift+trunc, only concern ourselves with low and high parts. This is all that was being used anyway. Signed-off-by: Richard Henderson <rth@twiddle.net>
2015-07-09cpu-exec: Purge all uses of ENV_GET_CPU()Peter Crosthwaite1-1/+1
Remove un-needed usages of ENV_GET_CPU() by converting the APIs to use CPUState pointers and retrieving the env_ptr as minimally needed. Scripted conversion for target-* change: for I in target-*/cpu.h; do sed -i \ 's/\(^int cpu_[^_]*_exec(\)[^ ][^ ]* \*s);$/\1CPUState *cpu);/' \ $I; done Signed-off-by: Peter Crosthwaite <crosthwaite.peter@gmail.com> Signed-off-by: Andreas Färber <afaerber@suse.de>
2015-07-09cpu: Change cpu_exec_init() arg to cpu, not envPeter Crosthwaite1-1/+1
The callers (most of them in target-foo/cpu.c) to this function all have the cpu pointer handy. Just pass it to avoid an ENV_GET_CPU() from core code (in exec.c). Cc: Paolo Bonzini <pbonzini@redhat.com> Cc: Richard Henderson <rth@twiddle.net> Cc: Peter Maydell <peter.maydell@linaro.org> Cc: "Edgar E. Iglesias" <edgar.iglesias@gmail.com> Cc: Eduardo Habkost <ehabkost@redhat.com> Cc: Michael Walle <michael@walle.cc> Cc: Leon Alrae <leon.alrae@imgtec.com> Cc: Anthony Green <green@moxielogic.com> Cc: Jia Liu <proljc@gmail.com> Cc: Alexander Graf <agraf@suse.de> Cc: Blue Swirl <blauwirbel@gmail.com> Cc: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Cc: Bastian Koppelmann <kbastian@mail.uni-paderborn.de> Cc: Guan Xuetao <gxt@mprc.pku.edu.cn> Cc: Max Filippov <jcmvbkbc@gmail.com> Reviewed-by: Andreas Färber <afaerber@suse.de> Reviewed-by: Aurelien Jarno <aurelien@aurel32.net> Signed-off-by: Peter Crosthwaite <crosthwaite.peter@gmail.com> Signed-off-by: Andreas Färber <afaerber@suse.de>
2015-07-09cpu: Add Error argument to cpu_exec_init()Bharata B Rao1-1/+1
Add an Error argument to cpu_exec_init() to let users collect the error. This is in preparation to change the CPU enumeration logic in cpu_exec_init(). With the new enumeration logic, cpu_exec_init() can fail if cpu_index values corresponding to max_cpus have already been handed out. Since all current callers of cpu_exec_init() are from instance_init, use error_abort Error argument to abort in case of an error. Signed-off-by: Bharata B Rao <bharata@linux.vnet.ibm.com> Reviewed-by: Eduardo Habkost <ehabkost@redhat.com> Reviewed-by: Igor Mammedov <imammedo@redhat.com> Reviewed-by: David Gibson <david@gibson.dropbear.id.au> Reviewed-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com> Acked-by: Paolo Bonzini <pbonzini@redhat.com> Signed-off-by: Peter Crosthwaite <crosthwaite.peter@gmail.com> Signed-off-by: Andreas Färber <afaerber@suse.de>
2015-06-29target-tricore: fix depositing bits from PCXI into ICRPaolo Bonzini1-2/+2
Spotted by Coverity, because (env->PCXI & MASK_PCXI_PCPN) >> 24 is always zero. The immediately preceding assignment is also wrong though. Signed-off-by: Paolo Bonzini <pbonzini@redhat.com> Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de> Message-Id: <1435147270-1040-1-git-send-email-pbonzini@redhat.com>
2015-06-22disas: Remove uses of CPU envPeter Crosthwaite1-1/+1
disas does not need to access the CPU env for any reason. Change the APIs to accept CPU pointers instead. Small change pattern needs to be applied to all target translate.c. This brings us closer to making disas.o a common-obj and less architecture specific in general. Cc: Richard Henderson <rth@twiddle.net> Cc: Peter Maydell <peter.maydell@linaro.org> Cc: "Edgar E. Iglesias" <edgar.iglesias@gmail.com> Cc: Paolo Bonzini <pbonzini@redhat.com> Cc: Eduardo Habkost <ehabkost@redhat.com> Cc: Michael Walle <michael@walle.cc> Cc: Aurelien Jarno <aurelien@aurel32.net> Cc: Leon Alrae <leon.alrae@imgtec.com> Cc: Jia Liu <proljc@gmail.com> Cc: Alexander Graf <agraf@suse.de> Cc: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Cc: Bastian Koppelmann <kbastian@mail.uni-paderborn.de> Cc: Guan Xuetao <gxt@mprc.pku.edu.cn> Cc: Max Filippov <jcmvbkbc@gmail.com> Reviewed-by: Richard Henderson <rth@twiddle.net> Reviewed-by: Eduardo Habkost <ehabkost@redhat.com> Signed-off-by: Peter Crosthwaite <crosthwaite.peter@gmail.com> Acked-by: Luiz Capitulino <lcapitulino@redhat.com> Signed-off-by: Markus Armbruster <armbru@redhat.com>
2015-05-30target-tricore: fix BOL_ST_H_LONGOFF using ldBastian Koppelmann1-1/+1
Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de> Message-Id: <1432289758-6250-4-git-send-email-kbastian@mail.uni-paderborn.de>
2015-05-30target-tricore: fix msub32_q producing the wrong overflow bitBastian Koppelmann1-11/+0
The inversion of the overflow bit as a special case, which was needed for the madd32_q instructions, does not apply for msub32_q instructions. So remove it. Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de> Message-Id: <1432289758-6250-3-git-send-email-kbastian@mail.uni-paderborn.de>
2015-05-30target-tricore: fix OPC2_32_RR_DVINIT_HU having write before use on the resultBastian Koppelmann1-1/+1
If the argument r1 was the same as the extended result register r3+1, we would overwrite r1 and then use it. Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de> Message-Id: <1432289758-6250-2-git-send-email-kbastian@mail.uni-paderborn.de>
2015-05-22target-tricore: add RR_DIV and RR_DIV_U instructions of the v1.6 ISABastian Koppelmann4-0/+74
Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de> Reviewed-by: Richard Henderson <rth@twiddle.net>
2015-05-22target-tricore: add FRET instructions of the v1.6 ISABastian Koppelmann2-0/+21
Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de> Reviewed-by: Richard Henderson <rth@twiddle.net>
2015-05-22target-tricore: add FCALL instructions of the v1.6 ISABastian Koppelmann2-0/+29
Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de> Reviewed-by: Richard Henderson <rth@twiddle.net>
2015-05-22target-tricore: add SYS_RESTORE instruction of the v1.6 ISABastian Koppelmann2-0/+11
Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de> Reviewed-by: Richard Henderson <rth@twiddle.net>
2015-05-22target-tricore: add RR_CRC32 instruction of the v1.6.1 ISABastian Koppelmann4-0/+19
This instruction was introduced by the new Aurix platform. Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de> Reviewed-by: Richard Henderson <rth@twiddle.net>
2015-05-22target-tricore: add SWAPMSK instructions of the v1.6.1 ISABastian Koppelmann2-0/+44
Those instruction were introduced in the new Aurix platform. Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de> Reviewed-by: Richard Henderson <rth@twiddle.net>
2015-05-22target-tricore: add CMPSWP instructions of the v1.6.1 ISABastian Koppelmann2-0/+40
Those instruction were introduced in the new Aurix platform. Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de> Reviewed-by: Richard Henderson <rth@twiddle.net>
2015-05-22target-tricore: Add SRC_MOV_E instruction of the v1.6 ISABastian Koppelmann1-2/+9
Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de> Reviewed-by: Richard Henderson <rth@twiddle.net>
2015-05-22target-tricore: introduce ISA v1.6.1 featureBastian Koppelmann2-3/+8
The aurix platform contains of several different cpu models and uses the 1.6.1 ISA. This patch changes the generic aurix model to the more specific tc27x cpu model and sets specific features. Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de> Reviewed-by: Richard Henderson <rth@twiddle.net>
2015-05-22target-tricore: Add ISA v1.3.1 cpu and fix tc1796 to using v1.3Bastian Koppelmann1-0/+8
Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de> Reviewed-by: Richard Henderson <rth@twiddle.net>
2015-05-11target-tricore: fix rfe not restoring the PCBastian Koppelmann1-0/+1
Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
2015-05-11target-tricore: fix rslcx restoring the upper context instead of the lowerBastian Koppelmann1-1/+1
Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
2015-05-11target-tricore: fix BO_OFF10_SEXT calculating the wrong offsetBastian Koppelmann1-1/+1
The lower part of the combined offset was sign extended and could lead to wrong results. Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
2015-05-11target-tricore: fix SLR_LD_W and SLR_LD_W_POSTINC insn being a 2 byte memory ↵Bastian Koppelmann1-2/+2
access insted of 4 Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
2015-05-11target-tricore: Fix LOOP using wrong register for compareBastian Koppelmann1-1/+1
Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
2015-04-30tcg: Delete unused cpu_pc_from_tb()Peter Crosthwaite1-5/+0
No code uses the cpu_pc_from_tb() function. Delete from tricore and arm which each provide an unused implementation. Update the comment in tcg.h to reflect that this is obsoleted by synchronize_from_tb. Signed-off-by: Peter Crosthwaite <crosthwaite.peter@gmail.com> Signed-off-by: Michael Tokarev <mjt@tls.msk.ru>
2015-04-04target-tricore: Fix check which was always falseStefan Weil1-1/+1
With a mask value of 0x00400000, the result will never be 1. This fixes a Coverity warning. Signed-off-by: Stefan Weil <sw@weilnetz.de> Signed-off-by: Michael Tokarev <mjt@tls.msk.ru>
2015-03-30target-tricore: fix CACHEA/I_POSTINC/PREINC using data register..Bastian Koppelmann1-4/+4
..for address calculation instead address registers. Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
2015-03-24target-tricore: properly fix dvinit_b/h_13Bastian Koppelmann1-30/+10
The TriCore documentation was wrong on how to calculate ovf bits for those two instructions, which I confirmed with real hardware (TC1796 chip). An ovf actually happens, if the result (without remainder) does not fit into 8/16 bits. Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
2015-03-24target-tricore: fix RRPW_DEXTR using wrong regBastian Koppelmann1-2/+2
RRPW_DEXTR used r1 for the low part and r2 for the high part. It should be the other way round. This also fixes that the result of the first shift was not saved in a temp and could overwrite registers that were needed for the second shift. Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
2015-03-24target-tricore: fix DVINIT_HU/BU calculating overflow before resultBastian Koppelmann1-12/+18
dvinit_hu/bu for ISA v1.3 calculate the higher part of the result, that is needed for the overflow bits, after calculating the overflow bits. Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
2015-03-24target-tricore: Fix two helper functions (clang warnings)Stefan Weil1-6/+6
clang report: target-tricore/op_helper.c:1247:24: warning: taking the absolute value of unsigned type 'uint32_t' (aka 'unsigned int') has no effect [-Wabsolute-value] target-tricore/op_helper.c:1248:25: warning: taking the absolute value of unsigned type 'uint32_t' (aka 'unsigned int') has no effect [-Wabsolute-value] target-tricore/op_helper.c:1249:19: warning: taking the absolute value of unsigned type 'uint32_t' (aka 'unsigned int') has no effect [-Wabsolute-value] target-tricore/op_helper.c:1297:24: warning: taking the absolute value of unsigned type 'uint32_t' (aka 'unsigned int') has no effect [-Wabsolute-value] target-tricore/op_helper.c:1298:25: warning: taking the absolute value of unsigned type 'uint32_t' (aka 'unsigned int') has no effect [-Wabsolute-value] target-tricore/op_helper.c:1299:19: warning: taking the absolute value of unsigned type 'uint32_t' (aka 'unsigned int') has no effect [-Wabsolute-value] Fix also the divisor which was taken from the wrong register (thanks to Peter Maydell for this hint). Cc: Bastian Koppelmann <kbastian@mail.uni-paderborn.de> Signed-off-by: Stefan Weil <sw@weilnetz.de> Message-Id: <1425739412-8144-1-git-send-email-sw@weilnetz.de> Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
2015-03-19Fix typos in commentsViswesh1-11/+11
Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Viswesh <visweshn92@gmail.com> Signed-off-by: Michael Tokarev <mjt@tls.msk.ru>
2015-03-16target-tricore: Add instructions of SYS opcode formatBastian Koppelmann4-0/+175
This adds only the non trap instructions. Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
2015-03-16target-tricore: Add instructions of RRRW opcode formatBastian Koppelmann1-0/+63
Reviewed-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
2015-03-16target-tricore: Add instructions of RRRR opcode formatBastian Koppelmann1-0/+56
Reviewed-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
2015-03-16target-tricore: Add instructions of RRR1 opcode format, which have 0xe3 as ↵Bastian Koppelmann4-2/+415
first opcode Add helpers helper_subadr_h/_ssov which subs one halfword and adds one halfword, rounds / and saturates each half word independently. Add microcode helper functions: * gen_msubad_h/ads_h: multiply two halfwords left justified and sub from the first one word and add the second one word / and saturate each resulting word independetly. * gen_msubadm_h/adms_h: multiply two halfwords in q-format left justified and sub from the first one word and add to the second one word / and saturate each resulting word independetly. * gen_msubadr32_h/32s_h: multiply two halfwords in q-format left justified and sub from the first one word and add to the second one word, round both results / and saturate each resulting word independetly. Reviewed-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
2015-03-16target-tricore: Add instructions of RRR1 opcode format, which have 0x63 as ↵Bastian Koppelmann4-2/+600
first opcode Add helpers: * msub64_q_ssov: multiply two 32 bit q-format number, sub the result from a 64 bit q-format number and saturate. * msub32_q_sub_ssov: sub two 64 bit q-format numbers and return a 32 bit result. * msubr_q_ssov: multiply two 32 bit q-format numbers, sub the result from a 32 bit q-format number and saturate. * msubr_q: multiply two 32 bit q-format numbers and sub the result from a 32 bit q-format number. Reviewed-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
2015-03-16target-tricore: Add instructions of RRR1 opcode format, which have 0xa3 as ↵Bastian Koppelmann4-24/+493
first opcode Add helpers: * sub64_ssov: subs two 64 bit values and saturates the result. * subr_h/_ssov: subs two halfwords from two words in q-format with rounding / and saturates each result independetly. Add microcode generator: * gen_sub64_d: adds two 64 bit values. * gen_msub_h/s_h: multiply four halfwords, sub each result left justfied from two word values / and saturate each result. * gen_msubm_h/s_h: multiply four halfwords, sub each result left justfied from two words values in q-format / and saturate each result. * gen_msubr32/64_h/s_h: multiply four halfwords, sub each result left justfied from two halftwords/words values in q-format / and saturate each result. Reviewed-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
2015-03-13tcg: Change translator-side labels to a pointerRichard Henderson1-4/+2
This is improved type checking for the translators -- it's no longer possible to accidentally swap arguments to the branch functions. Note that the code generating backends still manipulate labels as int. With notable exceptions, the scope of the change is just a few lines for each target, so it's not worth building extra machinery to do this change in per-target increments. Cc: Peter Maydell <peter.maydell@linaro.org> Cc: Edgar E. Iglesias <edgar.iglesias@gmail.com> Cc: Michael Walle <michael@walle.cc> Cc: Leon Alrae <leon.alrae@imgtec.com> Cc: Anthony Green <green@moxielogic.com> Cc: Jia Liu <proljc@gmail.com> Cc: Alexander Graf <agraf@suse.de> Cc: Aurelien Jarno <aurelien@aurel32.net> Cc: Blue Swirl <blauwirbel@gmail.com> Cc: Guan Xuetao <gxt@mprc.pku.edu.cn> Cc: Paolo Bonzini <pbonzini@redhat.com> Cc: Max Filippov <jcmvbkbc@gmail.com> Reviewed-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de> Signed-off-by: Richard Henderson <rth@twiddle.net>
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