summaryrefslogtreecommitdiff
path: root/target-tricore/translate.c
AgeCommit message (Expand)AuthorFilesLines
2015-10-07tcg: Remove gen_intermediate_code_pcRichard Henderson1-26/+5
2015-10-07tcg: Pass data argument to restore_state_to_opcRichard Henderson1-2/+3
2015-10-07tcg: Add TCG_MAX_INSNSRichard Henderson1-7/+13
2015-10-07target-*: Increment num_insns immediately after tcg_gen_insn_startRichard Henderson1-2/+1
2015-10-07target-*: Unconditionally emit tcg_gen_insn_startRichard Henderson1-0/+2
2015-09-11tlb: Add "ifetch" argument to cpu_mmu_index()Benjamin Herrenschmidt1-1/+1
2015-08-24tcg: Remove tcg_gen_trunc_i64_i32Richard Henderson1-10/+10
2015-08-24tcg: Split trunc_shr_i32 opcode into extr[lh]_i64_i32Richard Henderson1-6/+6
2015-06-22disas: Remove uses of CPU envPeter Crosthwaite1-1/+1
2015-05-30target-tricore: fix BOL_ST_H_LONGOFF using ldBastian Koppelmann1-1/+1
2015-05-30target-tricore: fix msub32_q producing the wrong overflow bitBastian Koppelmann1-11/+0
2015-05-30target-tricore: fix OPC2_32_RR_DVINIT_HU having write before use on the resultBastian Koppelmann1-1/+1
2015-05-22target-tricore: add RR_DIV and RR_DIV_U instructions of the v1.6 ISABastian Koppelmann1-0/+21
2015-05-22target-tricore: add FRET instructions of the v1.6 ISABastian Koppelmann1-0/+19
2015-05-22target-tricore: add FCALL instructions of the v1.6 ISABastian Koppelmann1-0/+26
2015-05-22target-tricore: add SYS_RESTORE instruction of the v1.6 ISABastian Koppelmann1-0/+10
2015-05-22target-tricore: add RR_CRC32 instruction of the v1.6.1 ISABastian Koppelmann1-0/+5
2015-05-22target-tricore: add SWAPMSK instructions of the v1.6.1 ISABastian Koppelmann1-0/+39
2015-05-22target-tricore: add CMPSWP instructions of the v1.6.1 ISABastian Koppelmann1-0/+35
2015-05-22target-tricore: Add SRC_MOV_E instruction of the v1.6 ISABastian Koppelmann1-2/+9
2015-05-11target-tricore: fix SLR_LD_W and SLR_LD_W_POSTINC insn being a 2 byte memory ...Bastian Koppelmann1-2/+2
2015-05-11target-tricore: Fix LOOP using wrong register for compareBastian Koppelmann1-1/+1
2015-03-30target-tricore: fix CACHEA/I_POSTINC/PREINC using data register..Bastian Koppelmann1-4/+4
2015-03-24target-tricore: fix RRPW_DEXTR using wrong regBastian Koppelmann1-2/+2
2015-03-24target-tricore: fix DVINIT_HU/BU calculating overflow before resultBastian Koppelmann1-12/+18
2015-03-19Fix typos in commentsViswesh1-11/+11
2015-03-16target-tricore: Add instructions of SYS opcode formatBastian Koppelmann1-0/+76
2015-03-16target-tricore: Add instructions of RRRW opcode formatBastian Koppelmann1-0/+63
2015-03-16target-tricore: Add instructions of RRRR opcode formatBastian Koppelmann1-0/+56
2015-03-16target-tricore: Add instructions of RRR1 opcode format, which have 0xe3 as fi...Bastian Koppelmann1-0/+327
2015-03-16target-tricore: Add instructions of RRR1 opcode format, which have 0x63 as fi...Bastian Koppelmann1-0/+440
2015-03-16target-tricore: Add instructions of RRR1 opcode format, which have 0xa3 as fi...Bastian Koppelmann1-0/+357
2015-03-13tcg: Change translator-side labels to a pointerRichard Henderson1-4/+2
2015-03-03target-tricore: Add instructions of RRR1 opcode format, which have 0xc3 as fi...Bastian Koppelmann1-0/+332
2015-03-03target-tricore: Add instructions of RRR1 opcode format, which have 0x43 as fi...Bastian Koppelmann1-0/+427
2015-03-03target-tricore: Add instructions of RRR1 opcode format, which have 0x83 as fi...Bastian Koppelmann1-0/+421
2015-03-03target-tricore: Add instructions of RRR2 opcode formatBastian Koppelmann1-14/+135
2015-03-03target-tricore: Fix RLC_ADDI, RLC_ADDIH using wrong microcode helperBastian Koppelmann1-2/+2
2015-02-12tcg: Introduce tcg_op_buf_count and tcg_op_buf_fullRichard Henderson1-3/+1
2015-02-12tcg: Move emit of INDEX_op_end into gen_tb_endRichard Henderson1-1/+0
2015-01-27target-tricore: Add instructions of RRR opcode formatBastian Koppelmann1-0/+150
2015-01-27target-tricore: Add instructions of RRPW opcode formatBastian Koppelmann1-0/+70
2015-01-27target-tricore: Add instructions of RR2 opcode formatBastian Koppelmann1-0/+37
2015-01-27target-tricore: Add instructions of RR1 opcode format, that have 0x93 as firs...Bastian Koppelmann1-0/+182
2015-01-26target-tricore: Fix bugs found by coverityBastian Koppelmann1-1/+2
2015-01-26target-tricore: Several translator and cpu model fixesBastian Koppelmann1-3/+3
2015-01-15target-tricore: Fix new typosStefan Weil1-1/+1
2015-01-09Merge remote-tracking branch 'remotes/bonzini/tags/for-upstream' into stagingPeter Maydell1-1/+1
2015-01-03gen-icount: check cflags instead of use_icount globalPaolo Bonzini1-1/+1
2014-12-21target-tricore: Add instructions of RR1 opcode format, that have 0xb3 as firs...Bastian Koppelmann1-0/+197
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-23 15:24:40 +0000