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AgeCommit message (Expand)AuthorFilesLines
2011-04-12target-sh4: get rid of CPU_{Float,Double}UAurelien Jarno2-158/+92
2011-04-10Fix conversions from pointer to tcg_target_longStefan Weil1-1/+1
2011-03-13inline cpu_halted into sole callerPaolo Bonzini1-10/+0
2011-03-03target-sh4: move intr_at_halt out of cpu_halted()Aurelien Jarno4-4/+4
2011-02-04target-sh4: fix negcAurelien Jarno1-2/+2
2011-01-26target-sh4: update PTEH upon MMU exceptionAlexandre Courbot1-0/+4
2011-01-26sh4: implement missing mmaped TLB read functionsAurelien Jarno2-0/+82
2011-01-26sh4: implement missing mmaped TLB write functionsAurelien Jarno2-3/+67
2011-01-25target-sh4: fix index of address read error exceptionAlexandre Courbot1-1/+1
2011-01-25target-sh4: fix TLB invalidation codeAlexandre Courbot1-2/+2
2011-01-16target-sh4: implement negc using TCGAurelien Jarno3-17/+15
2011-01-16target-sh4: use rotl/rotr when possibleAurelien Jarno1-5/+3
2011-01-15target-sh4: correct use of ! and &Aurelien Jarno1-2/+2
2011-01-14target-sh4: use setcond when possibleAurelien Jarno1-29/+27
2011-01-14target-sh4: log instructions start in TCG codeAurelien Jarno1-0/+4
2011-01-14target-sh4: simplify comparisons after a 'and' opAurelien Jarno1-3/+3
2011-01-14target-sh4: fix reset on r2dAurelien Jarno2-18/+16
2011-01-14target-sh4: optimize exceptionsAurelien Jarno2-15/+12
2011-01-14target-sh4: add ftrv instructionAurelien Jarno3-0/+38
2011-01-14target-sh4: add fipr instructionAurelien Jarno3-0/+33
2011-01-14target-sh4: implement FPU exceptionsAurelien Jarno1-22/+136
2011-01-14target-sh4: implement flush-to-zeroAurelien Jarno2-0/+2
2011-01-14target-sh4: define FPSCR constantsAurelien Jarno3-9/+37
2011-01-14target-sh4: use default-NaN modeAurelien Jarno1-0/+1
2011-01-11target-sh4: fix fpu disabled/illegal exceptionAurelien Jarno1-10/+18
2011-01-10target-sh4: improve TLBAurelien Jarno1-21/+44
2011-01-09target-sh4: implement writes to mmaped ITLBAurelien Jarno2-0/+21
2010-10-30target-xxx: Use fprintf_function (format checking)Stefan Weil2-2/+3
2010-07-12target-sh4: Add support for ldc & stc with sgrAlexandre Courbot1-0/+2
2010-07-12target-sh4: Split the LDST macro into 2 sub-macrosAlexandre Courbot1-2/+6
2010-07-03remove exec-all.h inclusion from cpu.hPaolo Bonzini1-1/+0
2010-07-03move cpu_pc_from_tb to target-*/exec.hPaolo Bonzini2-6/+6
2010-05-05target-sh4: Remove duplicate CPU log.Richard Henderson1-6/+0
2010-04-08remove TARGET_* defines from translate-all.cPaolo Bonzini1-0/+2
2010-03-18Replace assert(0) with abort() or cpu_abort()Blue Swirl3-5/+5
2010-03-17Large page TLB flushPaul Brook1-1/+2
2010-03-12Target specific usermode cleanupPaul Brook1-0/+2
2010-03-12Remove cpu_get_phys_page_debug from userspace emulationPaul Brook1-5/+0
2010-03-12Move TARGET_PHYS_ADDR_SPACE_BITS to target-*/cpu.h.Richard Henderson1-0/+3
2010-02-14Fix incorrect exception_index useBlue Swirl1-1/+1
2010-02-09target-sh4: MMU: separate execute and read/write permissionsAurelien Jarno1-21/+6
2010-02-09target-sh4: MMU: fix store queue addressesAurelien Jarno1-1/+1
2010-02-09target-sh4: MMU: remove dead codeAurelien Jarno1-18/+0
2010-02-09target-sh4: MMU: reduce the size of a TLB entryAurelien Jarno1-12/+11
2010-02-09target-sh4: MMU: optimize UTLB accessesAurelien Jarno1-24/+14
2010-02-09target-sh4: MMU: fix ITLB priviledge checkAurelien Jarno1-1/+1
2010-02-09target-sh4: MMU: simplify call to tlb_set_page()Aurelien Jarno1-6/+3
2010-02-09target-sh4: MMU: fix mem_idx computationAurelien Jarno1-1/+1
2010-02-09sh7750: handle MMUCR TI bitAurelien Jarno2-0/+20
2010-02-08target-sh4: minor optimisationsAurelien Jarno1-26/+26
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