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2009-03-07Fix off-by-one errors for Altivec and SPE registersaurel321-8/+8
Altivec and SPE both have 34 registers in their register sets, not 35 with a missing register 32. GDB would ask for register 32 of the Altivec (resp. SPE) registers and the code would claim it had zero width. The QEMU GDB stub code would then return an E14 to GDB, which would complain about not being sure whether p packets were supported or not. Signed-off-by: Nathan Froyd <froydnj@codesourcery.com> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net> git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6769 c046a42c-6fe2-441c-8c8c-71466251a162
2009-03-07Keep SLB in-CPUblueswir11-1/+1
Real 970 CPUs have the SLB not memory backed, but inside the CPU. This breaks bridge mode for 970 for now, but at least keeps us from overwriting physical addresses 0x0 - 0x300, rendering our interrupt handlers useless. I put in a stub for bridge mode operation that could be enabled easily, but for now it's safer to leave that off I guess (970fx doesn't have bridge mode AFAIK). Signed-off-by: Alexander Graf <alex@csgraf.de> git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6757 c046a42c-6fe2-441c-8c8c-71466251a162
2009-03-07Nop some SPRs on 970fxblueswir11-0/+12
Linux tries to access some SPRs on PPC64 boot. Let's just ignore those for the 970fx for now to make it happy. Signed-off-by: Alexander Graf <alex@csgraf.de> git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6751 c046a42c-6fe2-441c-8c8c-71466251a162
2009-03-03target-ppc: improve mfcr/mtcrfaurel321-1/+0
- use ctz32 instead of ffs - 1 - small optimisation of mtcrf - add the name of both opcodes Signed-off-by: Aurelien Jarno <aurelien@aurel32.net> git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6669 c046a42c-6fe2-441c-8c8c-71466251a162
2009-03-02kvm/powerpc: Add irq support for E500 coreaurel321-2/+3
Signed-off-by: Liu Yu <yu.liu@freescale.com> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net> git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6662 c046a42c-6fe2-441c-8c8c-71466251a162
2009-02-28Implement HIORblueswir11-8/+21
A real 970 CPU starts up with HIOR=0xfff00000 and triggers a reset exception, basically ending up at IP 0xfff001000. Later on this HIOR has to be set to 0 by the firmware in order to enable the OS to handle interrupts on its own. This patch maps HIOR to exec_prefix, which does the same thing internally in qemu already. It replaces the previous patch that changed the 970 initialization constants, as this is the clean solution to the same problem. Signed-off-by: Alexander Graf <alex@csgraf.de> git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6656 c046a42c-6fe2-441c-8c8c-71466251a162
2009-02-09target-ppc: Model e500v{1,2} CPUs more accuratelyaurel321-102/+125
The e500v1 chips only have single-precision floating point; don't say we support the double-precision floating-point instructions on such chips. Also add an e500v1 -cpu argument for a generic e500v1. Signed-off-by: Nathan Froyd <froydnj@codesourcery.com> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net> git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6576 c046a42c-6fe2-441c-8c8c-71466251a162
2009-02-09target-ppc: Model SPE floating-point instructions more accuratelyaurel321-9/+9
Single-precision and double-precision floating-point instructions should be separated into their own categories, since some chips only support single-precision instructions. Signed-off-by: Nathan Froyd <froydnj@codesourcery.com> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net> git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6575 c046a42c-6fe2-441c-8c8c-71466251a162
2009-02-05targets: remove error handling from qemu_malloc() callers (Avi Kivity)aliguori1-2/+0
Signed-off-by: Avi Kivity <avi@redhat.com> Signed-off-by: Anthony Liguori <aliguori@us.ibm.com> git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6530 c046a42c-6fe2-441c-8c8c-71466251a162
2009-02-03Add calls to initialize VSCR on appropriate machinesaurel321-0/+22
Signed-off-by: Nathan Froyd <froydnj@codesourcery.com> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net> git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6507 c046a42c-6fe2-441c-8c8c-71466251a162
2009-01-24target-ppc: Add SPE register read/write using XMLaurel321-0/+50
Don't read/write SPEFSCR until we figure out what to do about exceptions. Signed-off-by: Nathan Froyd <froydnj@codesourcery.com> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net> git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6425 c046a42c-6fe2-441c-8c8c-71466251a162
2009-01-24target-ppc: Add Altivec register read/write using XMLaurel321-0/+50
Signed-off-by: Nathan Froyd <froydnj@codesourcery.com> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net> git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6424 c046a42c-6fe2-441c-8c8c-71466251a162
2009-01-24target-ppc: Add float register read/write using XMLaurel321-0/+32
Signed-off-by: Nathan Froyd <froydnj@codesourcery.com> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net> git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6423 c046a42c-6fe2-441c-8c8c-71466251a162
2009-01-24target-ppc: Include gdbstub.haurel321-0/+1
Signed-off-by: Nathan Froyd <froydnj@codesourcery.com> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net> git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6422 c046a42c-6fe2-441c-8c8c-71466251a162
2009-01-04Update FSF address in GPL/LGPL boilerplateaurel321-1/+1
The attached patch updates the FSF address in the GPL/LGPL boilerplate in most GPL/LGPLed files, and also in COPYING.LIB. Signed-off-by: Stuart Brady <stuart.brady@gmail.com> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net> git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6162 c046a42c-6fe2-441c-8c8c-71466251a162
2008-12-22Use the ARRAY_SIZE() macro where appropriate.malc1-3/+3
Change from v1: Avoid changing the existing coding style in certain files. Signed-off-by: Stuart Brady <stuart.brady@gmail.com> git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6120 c046a42c-6fe2-441c-8c8c-71466251a162
2008-12-11target-ppc: rework exception codeaurel321-3/+3
... also remove two warnings. Signed-off-by: Aurelien Jarno <aurelien@aurel32.net> git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5989 c046a42c-6fe2-441c-8c8c-71466251a162
2008-12-07target-ppc: convert SPR accesses to TCGaurel321-132/+177
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net> git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5910 c046a42c-6fe2-441c-8c8c-71466251a162
2008-11-16Attached patch fixes a series of this warningblueswir11-1/+1
when compiling on NetBSD: warning: array subscript has type 'char' Signed-off-by: Christoph Egger <Christoph.Egger@amd.com> git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5727 c046a42c-6fe2-441c-8c8c-71466251a162
2008-10-21target-ppc: Convert XER accesses to TCGaurel321-2/+2
Define XER bits as a single register and access them individually to avoid defining 5 32-bit registers (TCG doesn't permit to map 8-bit registers). Signed-off-by: Aurelien Jarno <aurelien@aurel32.net> git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5500 c046a42c-6fe2-441c-8c8c-71466251a162
2008-09-20Suppress gcc 4.x -Wpointer-sign (included in -Wall) warningsblueswir11-9/+9
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5275 c046a42c-6fe2-441c-8c8c-71466251a162
2008-09-14ppc: Convert ctr, lr moves to TCGaurel321-4/+4
Introduce TCG variables cpu_{ctr,lr} and replace op_{load,store}_{lr,ctr} with tcg_gen_mov_tl. Signed-off-by: Andreas Faerber <andreas.faerber@web.de> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net> git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5217 c046a42c-6fe2-441c-8c8c-71466251a162
2008-08-30Fix some warnings that would be generated by gcc -Wredundant-declsblueswir11-2/+0
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5115 c046a42c-6fe2-441c-8c8c-71466251a162
2007-12-10Fix PowerPC 74xx definitions.j_mayer1-47/+225
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3798 c046a42c-6fe2-441c-8c8c-71466251a162
2007-11-21Fix PowerPC 7xx definitions.j_mayer1-132/+612
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3713 c046a42c-6fe2-441c-8c8c-71466251a162
2007-11-19Remove shared macro used to define PowerPC implementations instructions sets:j_mayer1-172/+480
tend more to propagate bugged definition than simplify the code. Check and fix PowerPC 6xx implementations definitions. Misc fixes in PowerPC CPU list. git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3707 c046a42c-6fe2-441c-8c8c-71466251a162
2007-11-19PowerPC 620 MMU do not have the same exact behavior as standardj_mayer1-3/+6
64 bits PowerPC ones. git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3706 c046a42c-6fe2-441c-8c8c-71466251a162
2007-11-19New PowerPC CPU flag to define the decrementer and time-base source clock.j_mayer1-39/+67
Use it to properly initialize the clock for the PreP target. git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3701 c046a42c-6fe2-441c-8c8c-71466251a162
2007-11-17Improve PowerPC instructions set dump.j_mayer1-6/+44
Remove meaningless define from cpu.h Misc cleanups. git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3682 c046a42c-6fe2-441c-8c8c-71466251a162
2007-11-17Add definitions for Freescale PowerPC implementations,j_mayer1-1259/+2850
ie MPC5xx, MPC8xx, e200, e300, e500 and e600 cores. Make those CPUs and PowerPC 440 available for user-mode emulation, thus providing a way of testing their implementation specific instructions. git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3681 c046a42c-6fe2-441c-8c8c-71466251a162
2007-11-17Define Freescale cores specific MMU model, exceptions and input bus.j_mayer1-4/+13
(but do not provide any actual implementation). git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3680 c046a42c-6fe2-441c-8c8c-71466251a162
2007-11-17A little more granularity in PowerPC instructions definition is neededj_mayer1-21/+25
in order to implement Freescale cores. Fix efsadd / efssub opcodes. git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3679 c046a42c-6fe2-441c-8c8c-71466251a162
2007-11-17Make the PowerPC MMU model, exception model and input bus modelj_mayer1-4/+3
typedefed enums. git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3660 c046a42c-6fe2-441c-8c8c-71466251a162
2007-11-17Always make all PowerPC exception definitions visible.j_mayer1-2/+0
Always make the hypervisor timers available. Remove all TARGET_PPC64H checks, keeping a few if (0) tests for cases that cannot be properly handled with the current PowerPC CPU definition. git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3656 c046a42c-6fe2-441c-8c8c-71466251a162
2007-11-14Reorganize PowerPC instructions categories, add icbi separate case.j_mayer1-4/+6
Fix frsqrtes instruction opcode. git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3636 c046a42c-6fe2-441c-8c8c-71466251a162
2007-11-12Add PVR and SPR definition for most embedded PowerPC from Freescale.j_mayer1-59/+309
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3632 c046a42c-6fe2-441c-8c8c-71466251a162
2007-11-10Allow selection of PowerPC CPU giving a PVR.j_mayer1-371/+420
Remove unused pvr_mask field from CPU definition. git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3571 c046a42c-6fe2-441c-8c8c-71466251a162
2007-11-10added cpu_model parameter to cpu_init()bellard1-21/+11
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3562 c046a42c-6fe2-441c-8c8c-71466251a162
2007-11-04PowerPC 601 need specific callbacks for its BATs setup.j_mayer1-1/+10
Implement PowerPC 601 HID0 register, needed for little-endian mode support. As a consequence, we need to merge hflags coming from MSR with other ones. Use little-endian mode from hflags instead of MSR during code translation. git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3524 c046a42c-6fe2-441c-8c8c-71466251a162
2007-11-03Fix PowerPC high BATs access: BAT number was incorrect.j_mayer1-3/+3
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3519 c046a42c-6fe2-441c-8c8c-71466251a162
2007-11-03PowerPC MMU and exception fixes:j_mayer1-31/+31
* PowerPC 601 (and probably POWER/POWER2) uses a different BAT format than later PowerPC implementation. * Bugfix in BATs check: must not stop after 4 BATs when more are provided. * Enable POWER 'rac' instruction. * Fix exception prefix for all supported PowerPC implementations. * Fix exceptions, MMU model and bus model for PowerPC 601 & 620. * Enable PowerPC 620 as it could mostly boot a PreP target. git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3518 c046a42c-6fe2-441c-8c8c-71466251a162
2007-10-25Implement power-management for all defined PowerPC CPUs.j_mayer1-7/+172
Fix PowerPC 970MP definition. git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3440 c046a42c-6fe2-441c-8c8c-71466251a162
2007-10-25Allow selection of all defined PowerPC 74xx (aka G4) CPUs.j_mayer1-36/+0
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3437 c046a42c-6fe2-441c-8c8c-71466251a162
2007-10-14There is no need of a specific MMU model for PowerPC 601.j_mayer1-4/+1
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3392 c046a42c-6fe2-441c-8c8c-71466251a162
2007-10-08Remove synonymous in PowerPC MSR bits definitions.j_mayer1-39/+171
Fix MSR EP bit buggy definition. Remove unuseful MSR flags. Fix MSR bits and flags definitions for most supported PowerPC implementations. Add MSR definitions/flags constistency checks and optional dump. git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3354 c046a42c-6fe2-441c-8c8c-71466251a162
2007-10-08Real-mode only PowerPC 40x do not have any TLBs.j_mayer1-1/+0
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3353 c046a42c-6fe2-441c-8c8c-71466251a162
2007-10-08Implement exception prefix feature for PowerPC 601.j_mayer1-1/+1
Fix PowerPC 601 hardware reset vector. git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3352 c046a42c-6fe2-441c-8c8c-71466251a162
2007-10-08Add missing exception vectors for PowerPC 7x5.j_mayer1-1/+27
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3351 c046a42c-6fe2-441c-8c8c-71466251a162
2007-10-07Work-around C89 and/or "old" gcc unspecified behavior (#if in macro calls).j_mayer1-18/+9
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3350 c046a42c-6fe2-441c-8c8c-71466251a162
2007-10-07Reorganize the CPUPPCState structure to group features.j_mayer1-3/+46
Add #ifdef to avoid compiling not relevant resources: - MMU related stuff for user-mode only targets - PowerPC 64 only resources for PowerPC 32 targets - embedded PowerPC extensions for non-ppcemb targets. git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3343 c046a42c-6fe2-441c-8c8c-71466251a162
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