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AgeCommit message (Expand)AuthorFilesLines
2014-11-03target-mips: add MSA 2RF format instructionsYongbok Kim3-0/+621
2014-11-03target-mips: add MSA VEC/2R format instructionsYongbok Kim3-0/+265
2014-11-03target-mips: add MSA 3RF format instructionsYongbok Kim3-0/+1699
2014-11-03target-mips: add MSA ELM format instructionsYongbok Kim3-0/+290
2014-11-03target-mips: add MSA 3R format instructionsYongbok Kim3-0/+963
2014-11-03target-mips: add MSA BIT format instructionsYongbok Kim3-0/+297
2014-11-03target-mips: add MSA I5 format instructionYongbok Kim3-0/+232
2014-11-03target-mips: add MSA I8 format instructionsYongbok Kim3-2/+156
2014-11-03target-mips: add MSA branch instructionsYongbok Kim1-114/+220
2014-11-03target-mips: add msa_helper.cYongbok Kim2-1/+50
2014-11-03target-mips: add msa_reset(), global msa registerYongbok Kim2-0/+90
2014-11-03target-mips: add MSA opcode enumYongbok Kim1-0/+245
2014-11-03target-mips: stop translation after ctc1Yongbok Kim1-0/+6
2014-11-03target-mips: remove duplicated mips/ieee mapping functionYongbok Kim3-9/+6
2014-11-03target-mips: add MSA exceptionsYongbok Kim1-0/+10
2014-11-03target-mips: add MSA defines and data structureYongbok Kim3-2/+52
2014-11-03target-mips: enable features in MIPS64R6-generic CPULeon Alrae1-2/+9
2014-11-03target-mips: correctly handle access to unimplemented CP0 registerLeon Alrae1-278/+260
2014-11-03target-mips: add restrictions for possible values in registersLeon Alrae1-17/+53
2014-11-03target-mips: CP0_Status.CU0 no longer allows the user to access CP0Leon Alrae1-1/+2
2014-11-03target-mips: implement forbidden slotLeon Alrae2-36/+76
2014-11-03target-mips: add Config5.SBRILeon Alrae2-3/+32
2014-11-03target-mips: update cpu_save/cpu_load to support new registersLeon Alrae2-2/+26
2014-11-03target-mips: add BadInstr and BadInstrP supportLeon Alrae4-11/+133
2014-11-03target-mips: add TLBINV supportLeon Alrae6-8/+92
2014-11-03target-mips: add new Read-Inhibit and Execute-Inhibit exceptionsLeon Alrae2-2/+28
2014-11-03target-mips: update PageGrain and m{t,f}c0 EntryLo{0,1}Leon Alrae5-5/+57
2014-11-03target-mips: add RI and XI fields to TLB entryLeon Alrae3-1/+29
2014-11-03target-mips: distinguish between data load and instruction fetchLeon Alrae1-11/+10
2014-11-03target-mips: add KScratch registersLeon Alrae2-0/+47
2014-10-24target-mips: add ULL suffix in bitswap to avoid compiler warningLeon Alrae1-6/+6
2014-10-14target-mips: Remove unused gen_load_ACX, gen_store_ACX and cpu_ACXPeter Maydell1-19/+1
2014-10-14target-mips/dsp_helper.c: Add ifdef guards around various functionsPeter Maydell1-1/+16
2014-10-14target-mips/translate.c: Add ifdef guard around check_mips64()Peter Maydell1-0/+2
2014-10-14target-mips/op_helper.c: Remove unused do_lbu() functionPeter Maydell1-1/+0
2014-10-14target-mips/dsp_helper.c: Remove unused function get_DSPControl_24()Peter Maydell1-9/+0
2014-10-14target-mips: fix broken MIPS16 and microMIPSYongbok Kim2-188/+123
2014-10-14target-mips/translate.c: Update OPC_SYNCIDongxue Zhang1-1/+6
2014-10-14target-mips: define a new generic CPU supporting MIPS64 Release 6 ISALeon Alrae1-0/+30
2014-10-14target-mips: remove JR, BLTZAL, BGEZAL and add NAL, BAL instructionsYongbok Kim1-2/+16
2014-10-14target-mips: do not allow Status.FR=0 mode in 64-bit FPULeon Alrae1-0/+6
2014-10-14target-mips: add new Floating Point Comparison instructionsYongbok Kim3-2/+342
2014-10-14target-mips: add new Floating Point instructionsLeon Alrae3-44/+521
2014-10-14target-mips: add AUI, LSA and PCREL instruction familiesLeon Alrae1-14/+189
2014-10-13target-mips: add compact and CP1 branchesYongbok Kim1-14/+459
2014-10-13target-mips: add ALIGN, DALIGN, BITSWAP and DBITSWAP instructionsYongbok Kim3-12/+136
2014-10-13target-mips: Status.UX/SX/KX enable 32-bit address wrappingLeon Alrae2-9/+15
2014-10-13target-mips: move CLO, DCLO, CLZ, DCLZ, SDBBP and free special2 in R6Leon Alrae1-59/+62
2014-10-13target-mips: redefine Integer Multiply and Divide instructionsLeon Alrae1-21/+322
2014-10-13target-mips: move PREF, CACHE, LLD and SCD instructionsLeon Alrae1-1/+28
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