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AgeCommit message (Expand)AuthorFilesLines
2015-11-17target-i386: Disable rdtscp on Opteron_G* CPU modelsEduardo Habkost1-4/+8
2015-11-17target-i386: Fix mulx for identical target regsRichard Henderson1-1/+3
2015-11-06target-i386: Add clflushopt/clwb/pcommit to TCG_7_0_EBX_FEATURESXiao Guangrong1-1/+3
2015-11-06target-i386: tcg: Check right CPUID bits for clflushopt/pcommitEduardo Habkost1-8/+20
2015-11-06target-i386: tcg: Accept clwb instructionEduardo Habkost1-1/+12
2015-11-05target-i386: Enable clflushopt/clwb/pcommit instructionsXiao Guangrong2-2/+5
2015-11-05target-i386: Remove POPCNT from qemu64 and qemu32 CPU modelsEduardo Habkost1-2/+2
2015-11-05target-i386: Remove ABM from qemu64 CPU modelEduardo Habkost1-2/+1
2015-11-05target-i386: Remove SSE4a from qemu64 CPU modelEduardo Habkost1-1/+1
2015-11-05kvmclock: add a new function to update env->tsc.Liang Li2-0/+46
2015-11-04osdep: Rename qemu_{get, set}_version() to qemu_{, set_}hw_version()Eduardo Habkost1-1/+1
2015-11-04target-i386: fix pcmpxstrx equal-ordered (strstr) modePaolo Bonzini1-2/+2
2015-10-28target-*: Advance pc after recognizing a breakpointRichard Henderson1-0/+5
2015-10-27target-i386: Enable "check" mode by defaultEduardo Habkost1-1/+1
2015-10-27target-i386: Don't left shift negative constantEduardo Habkost1-1/+1
2015-10-23target-i386: Use 1UL for bit shiftEduardo Habkost1-1/+1
2015-10-23target-i386: Add DE to TCG_FEATURESEduardo Habkost1-1/+1
2015-10-23target-i386: Ensure always-1 bits on DR6 can't be clearedEduardo Habkost1-1/+1
2015-10-23target-i386: Check CR4[DE] for processing DR4/DR5Richard Henderson4-11/+50
2015-10-23target-i386: Handle I/O breakpointsEduardo Habkost4-28/+94
2015-10-23target-i386: Optimize setting dr[0-3]Richard Henderson1-3/+8
2015-10-23target-i386: Move hw_*breakpoint_* functionsRichard Henderson2-28/+28
2015-10-23target-i386: Ensure bit 10 on DR7 is never clearedEduardo Habkost1-0/+2
2015-10-23target-i386: Re-introduce optimal breakpoint removalRichard Henderson1-6/+28
2015-10-23target-i386: Introduce cpu_x86_update_dr7Richard Henderson4-22/+27
2015-10-23target-i386: Disable cache info passthrough by defaultEduardo Habkost1-3/+1
2015-10-23target-i386: allow any alignment for SMBASEPaolo Bonzini1-2/+2
2015-10-19kvm: Allow the Hyper-V vendor ID to be specifiedAlex Williamson3-1/+15
2015-10-19kvm: Move x86-specific functions into target-i386/kvm.cThomas Huth1-5/+26
2015-10-19kvm: Pass PCI device pointer to MSI routing functionsPavel Fedin1-1/+1
2015-10-12target-i386/kvm: Hyper-V HV_X64_MSR_VP_RUNTIME supportAndrey Smetanin5-1/+43
2015-10-12target-i386/kvm: set Hyper-V features cpuid bit HV_X64_MSR_VP_INDEX_AVAILABLEAndrey Smetanin3-1/+12
2015-10-12target-i386/kvm: Hyper-V HV_X64_MSR_RESET supportAndrey Smetanin3-2/+12
2015-10-09qdev: Protect device-list-properties against broken devicesMarkus Armbruster1-0/+8
2015-10-07tcg: Remove gen_intermediate_code_pcRichard Henderson1-44/+5
2015-10-07tcg: Pass data argument to restore_state_to_opcRichard Henderson1-20/+6
2015-10-07tcg: Add TCG_MAX_INSNSRichard Henderson1-1/+5
2015-10-07target-*: Drop cpu_gen_code defineRichard Henderson1-1/+0
2015-10-07target-i386: Add cc_op state to insn_startRichard Henderson2-1/+2
2015-10-07target-*: Introduce and use cpu_breakpoint_testRichard Henderson1-10/+7
2015-10-07target-*: Increment num_insns immediately after tcg_gen_insn_startRichard Henderson1-2/+3
2015-10-07target-*: Unconditionally emit tcg_gen_insn_startRichard Henderson1-3/+2
2015-10-07tcg: Rename debug_insn_start to insn_startRichard Henderson1-1/+1
2015-10-02cpu/apic: drop icc bus/bridgeChen Fan1-8/+1
2015-10-02apic: move APIC's MMIO region mapping into APICChen Fan1-0/+15
2015-10-02Correctly re-init EFER state during INIT IPIBill Paul1-1/+1
2015-10-02target-i386: add ABM to Haswell* and Broadwell* CPU modelsPaolo Bonzini1-4/+4
2015-10-02target-i386: get/put MSR_TSC_AUX across reset and migrationAmit Shah1-0/+14
2015-10-02target-i386: Make check_hw_breakpoints staticRichard Henderson2-2/+1
2015-10-02target-i386: Move breakpoint related functions to new fileRichard Henderson4-163/+183
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