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AgeCommit message (Expand)AuthorFilesLines
2014-10-06gdbstub: Allow target CPUs to specify watchpoint STOP_BEFORE_ACCESS flagPeter Maydell1-0/+1
2014-09-29target-arm: Add support for VIRQ and VFIQEdgar E. Iglesias5-14/+76
2014-09-29target-arm: Add IRQ and FIQ routing to EL2 and 3Edgar E. Iglesias2-0/+27
2014-09-29target-arm: A64: Emulate the SMC insnEdgar E. Iglesias7-0/+51
2014-09-29target-arm: Add a Hypervisor Trap exception typeEdgar E. Iglesias4-0/+4
2014-09-29target-arm: A64: Emulate the HVC insnEdgar E. Iglesias7-10/+81
2014-09-29target-arm: A64: Correct updates to FAR and ESR on exceptionsEdgar E. Iglesias1-4/+3
2014-09-29target-arm: Don't take interrupts targeting lower ELsEdgar E. Iglesias1-0/+7
2014-09-29target-arm: Break out exception masking to a separate funcEdgar E. Iglesias2-5/+17
2014-09-29target-arm: A64: Refactor aarch64_cpu_do_interruptEdgar E. Iglesias3-11/+33
2014-09-29target-arm: Add SCR_EL3Edgar E. Iglesias2-3/+51
2014-09-29target-arm: Add HCR_EL2Edgar E. Iglesias2-0/+70
2014-09-29target-arm: Don't handle c15_cpar changes via tb_flush()Peter Maydell6-30/+44
2014-09-29target-arm: Implement handling of breakpoint firingPeter Maydell2-15/+66
2014-09-29target-arm: Implement setting guest breakpointsPeter Maydell5-2/+136
2014-09-25target-arm: Use cpu_exec_interrupt qom hookRichard Henderson3-0/+36
2014-09-12target-arm: Make *IS TLB maintenance ops affect all CPUsPeter Maydell1-12/+89
2014-09-12target-arm: Push legacy wildcard TLB ops back into v6Peter Maydell1-47/+55
2014-09-12target-arm: Implement minimal DBGVCR, OSDLR_EL1, MDCCSR_EL0Peter Maydell1-0/+19
2014-09-12target-arm: Remove comment about MDSCR_EL1 being dummy implementationPeter Maydell1-3/+1
2014-09-12target-arm: Set DBGDSCR.MOE for debug exceptions taken to AArch32Peter Maydell1-0/+26
2014-09-12target-arm: Implement handling of fired watchpointsPeter Maydell4-1/+204
2014-09-12target-arm: Move extended_addresses_enabled() to internals.hPeter Maydell2-11/+11
2014-09-12target-arm: Implement setting of watchpointsPeter Maydell5-3/+149
2014-09-12target-arm: Fix broken indentation in arm_cpu_reest()Martin Galvan1-1/+1
2014-09-12target-arm: Fix resetting issues on ARMv7-M CPUsMartin Galvan1-10/+22
2014-08-29target-arm: Implement pmccfiltr_write functionAlistair Francis1-0/+9
2014-08-29target-arm: Remove old code and replace with new functionsAlistair Francis1-23/+4
2014-08-29target-arm: Implement pmccntr_sync functionAlistair Francis2-0/+34
2014-08-29target-arm: Add arm_ccnt_enabled functionAlistair Francis1-0/+12
2014-08-29target-arm: Implement PMCCNTR_EL0 and related registersAlistair Francis2-8/+42
2014-08-29arm: Implement PMCCNTR 32b read-modify-writePeter Crosthwaite1-1/+10
2014-08-29target-arm: Make the ARM PMCCNTR register 64-bitAlistair Francis2-11/+10
2014-08-29target-arm: Correct Cortex-A57 ISAR5 and AA64ISAR0 ID register valuesPeter Maydell1-1/+2
2014-08-29target-arm: Fix regression that disabled VFP for ARMv5 CPUsPeter Maydell1-1/+8
2014-08-19arm: cortex-a9: Fix cache-line size and associativityPeter Crosthwaite1-2/+2
2014-08-19arm/virt: Use PSCI v0.2 function IDs in the DT when KVM uses PSCI v0.2Christoffer Dall1-0/+27
2014-08-19target-arm: Rename QEMU PSCI v0.1 definitionsChristoffer Dall1-11/+11
2014-08-19target-arm: Implement MDSCR_EL1 as having statePeter Maydell1-1/+3
2014-08-19target-arm: Implement ARMv8 single-stepping for AArch32 codePeter Maydell2-2/+95
2014-08-19target-arm: Implement ARMv8 single-step handling for A64 codePeter Maydell6-5/+131
2014-08-19target-arm: A64: Avoid duplicate exit_tb(0) in non-linked goto_tbPeter Maydell1-2/+3
2014-08-19target-arm: Set PSTATE.SS correctly on exception return from AArch64Peter Maydell2-0/+81
2014-08-19target-arm: Correctly handle PSTATE.SS when taking exception to AArch32Peter Maydell1-0/+4
2014-08-19target-arm: Don't allow AArch32 to access RES0 CPSR bitsPeter Maydell3-9/+18
2014-08-19target-arm: Adjust debug ID registers per-CPUPeter Maydell4-7/+31
2014-08-19target-arm: Provide both 32 and 64 bit versions of debug registersPeter Maydell1-14/+20
2014-08-19target-arm: Allow STATE_BOTH reginfo descriptions for more than cp14Peter Maydell1-3/+8
2014-08-19target-arm: Collect up the debug cp register definitionsPeter Maydell1-32/+53
2014-08-19target-arm: Fix return address for A64 BRK instructionsPeter Maydell1-1/+1
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