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AgeCommit message (Expand)AuthorFilesLines
2016-05-12target-arm: Avoid unnecessary TLB flush on TCR_EL2, TCR_EL3 writesPeter Maydell1-4/+8
2016-05-12ARM: Factor out ARM on/off PSCI control functionsJean-Christophe DUBOIS4-63/+307
2016-05-12target-arm/translate-a64.c: Unify some of the ldst_reg decodingEdgar E. Iglesias1-18/+23
2016-05-12target-arm/translate-a64.c: Use extract32 in disas_ldst_reg_imm9Edgar E. Iglesias1-2/+2
2016-05-12target-arm: Split data abort syndrome generatorPeter Maydell2-5/+25
2016-05-12target-arm: Fix descriptor address masking in ARM address translationSergey Sorokin1-18/+11
2016-05-12target-arm: Stage 2 permission fault was fixed in AArch32 stateSergey Sorokin1-1/+3
2016-04-04target-arm: Make the 64-bit version of VTCR do the migrationPeter Maydell1-1/+5
2016-04-04target-arm: Remove incorrect ALIAS tags from ESR_EL2 and ESR_EL3Peter Maydell1-2/+0
2016-04-04target-arm: Correctly reset SCTLR_EL3 for 64-bit CPUsPeter Maydell1-10/+13
2016-03-30arm: implement query-gic-capabilitiesPeter Xu1-1/+57
2016-03-30arm: enhance kvm_arm_create_scratch_host_vcpuPeter Xu2-3/+18
2016-03-30arm: qmp: add query-gic-capabilities interfacePeter Xu2-1/+29
2016-03-22target-arm: dfilter support for in_asmAlex Bennée2-2/+4
2016-03-22util: move declarations out of qemu-common.hVeronia Bahaa1-0/+1
2016-03-22include/qemu/osdep.h: Don't include qapi/error.hMarkus Armbruster2-0/+2
2016-03-16target-arm: Fix translation level on early translation faultsSergey Sorokin1-10/+12
2016-03-16target-arm: Implement MRS (banked) and MSR (banked) instructionsPeter Maydell3-3/+366
2016-03-04target-arm: Only trap SRS from S-EL1 if specified mode is MONRalf-Philipp Weinmann1-1/+2
2016-03-04target-arm: implement BE32 mode in system emulationPaolo Bonzini2-18/+73
2016-03-04target-arm: implement setendPaolo Bonzini3-8/+12
2016-03-04target-arm: introduce tbflag for endiannessPeter Crosthwaite3-2/+9
2016-03-04target-arm: a64: Add endianness supportPeter Crosthwaite1-19/+30
2016-03-04target-arm: introduce disas flag for endiannessPaolo Bonzini3-15/+26
2016-03-04target-arm: pass DisasContext to gen_aa32_ld*/st*Paolo Bonzini1-128/+142
2016-03-04target-arm: implement SCTLR.EEPeter Crosthwaite1-2/+21
2016-03-04linux-user: arm: handle CPSR.E correctly in strex emulationPaolo Bonzini1-0/+11
2016-03-04arm: cpu: handle BE32 user-mode as BEPeter Crosthwaite1-1/+16
2016-03-04target-arm: cpu: Move cpu_is_big_endian to headerPeter Crosthwaite2-16/+22
2016-03-04target-arm: implement SCTLR.B, drop bswap_codePaolo Bonzini7-29/+60
2016-03-04target-arm: Correct handling of writes to CPSR mode bits from gdb in usermodePeter Maydell1-2/+9
2016-03-01tcg: Add type for vCPU pointersLluís Vilanova2-2/+2
2016-02-26target-arm: Make reserved ranges in ID_AA64* spaces RAZ, not UNDEFPeter Maydell2-7/+122
2016-02-26target-arm: Mark CNTHP_TVAL_EL2 as ARM_CP_NO_RAWEdgar E. Iglesias1-1/+1
2016-02-26target-arm: Implement MDCR_EL3.TPM and MDCR_EL2.TPM trapsPeter Maydell1-7/+36
2016-02-26target-arm: Fix handling of SDCR for 32-bit codePeter Maydell2-8/+19
2016-02-26target-arm: Make Monitor->NS PL1 mode changes illegal if HCR.TGE is 1Peter Maydell1-0/+10
2016-02-26target-arm: Make mode switches from Hyp via CPS and MRS illegalPeter Maydell1-2/+10
2016-02-26target-arm: In v8, make illegal AArch32 mode changes set PSTATE.ILPeter Maydell1-3/+12
2016-02-26target-arm: Forbid mode switch to Mon from Secure EL1Peter Maydell1-1/+1
2016-02-26target-arm: Add Hyp mode checks to bad_mode_switch()Peter Maydell1-0/+3
2016-02-26target-arm: Add comment about not implementing NSACR.RFRPeter Maydell1-0/+3
2016-02-26target-arm: In cpsr_write() ignore mode switches from User modePeter Maydell1-0/+1
2016-02-26target-arm: Raw CPSR writes should skip checks and bank switchingPeter Maydell4-6/+7
2016-02-26target-arm: Add write_type argument to cpsr_write()Peter Maydell7-10/+20
2016-02-26target-arm: Give CPSR setting on 32-bit exception return its own helperPeter Maydell3-3/+10
2016-02-23all: Clean up includesPeter Maydell2-2/+0
2016-02-18target-arm: Add PMUSERENR_EL0 registerAlistair Francis1-0/+6
2016-02-18target-arm: Add the pmovsclr_el0 and pmintenclr_el1 registersAlistair Francis1-0/+12
2016-02-18target-arm: Add the pmceid0 and pmceid1 registersAlistair Francis4-0/+22
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