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2010-03-27target-arm: disable PAGE_EXEC for XN pagesRabin Vincent1-3/+7
Don't set PAGE_EXEC for XN pages, to avoid a bypass of XN protection checking if the page is already in the TLB. Signed-off-by: Rabin Vincent <rabin@rab.in> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2010-03-23target-arm: Fix handling of AL condition in IT instructionJohan Bengtsson1-3/+5
Do not try to insert a conditional jump over next instruction when the condition code is AL as this will trigger an internal error. Signed-off-by: Johan Bengtsson <teofrastius@gmail.com> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2010-03-17Large page TLB flushPaul Brook1-21/+27
QEMU uses a fixed page size for the CPU TLB. If the guest uses large pages then we effectively split these into multiple smaller pages, and populate the corresponding TLB entries on demand. When the guest invalidates the TLB by virtual address we must invalidate all entries covered by the large page. However the address used to invalidate the entry may not be present in the QEMU TLB, so we do not know which regions to clear. Implementing a full vaiable size TLB is hard and slow, so just keep a simple address/mask pair to record which addresses may have been mapped by large pages. If the guest invalidates this region then flush the whole TLB. Signed-off-by: Paul Brook <paul@codesourcery.com>
2010-03-13target-arm: make RFE usable with any registerAdam Lackorzynski1-1/+1
The rfe instruction can be used with any register, not just sp. Adjust the condition check accordingly. Signed-off-by: Adam Lackorzynski <adam@os.inf.tu-dresden.de> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2010-03-12Remove cpu_get_phys_page_debug from userspace emulationPaul Brook1-5/+0
cpu_get_phys_page_debug makes no sense for userspace emulation, so remove it. Signed-off-by: Paul Brook <paul@codesourcery.com>
2010-03-12Move TARGET_PHYS_ADDR_SPACE_BITS to target-*/cpu.h.Richard Henderson1-0/+3
Removes a set of ifdefs from exec.c. Introduce TARGET_VIRT_ADDR_SPACE_BITS for all targets other than Alpha. This will be used for page_find_alloc, which is supposed to be using virtual addresses in the first place. Signed-off-by: Richard Henderson <rth@twiddle.net>
2010-03-06target-arm: Fix missing 'return' in SRS handling.Adam Lackorzynski1-0/+1
There's a return missing in the srs handling which leads to srs always being treated an an invalid op. Signed-off-by: Adam Lackorzynski <adam@os.inf.tu-dresden.de> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2010-02-28target-arm: neon vshll instruction fixJuha Riihimäki1-0/+1
implementation only widened the 32bit source vector elements into a 64bit destination vector but forgot to perform the actual shifting operation. Signed-off-by: Juha Riihimäki <juha.riihimaki@nokia.com> Signed-off-by: Riku Voipio <riku.voipio@nokia.com> Acked-by: Laurent Desnogues <laurent.desnogues@gmail.com> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2010-02-28target-arm: neon - fix VRADDHN/VRSUBHN vs VADDHN/VSUBHNRiku Voipio1-2/+2
The rounding/truncating options were inverted. truncating was done when rounding was meant and vice verse. Signed-off-by: Riku Voipio <riku.voipio@nokia.com> Acked-by: Laurent Desnogues <laurent.desnogues@gmail.com> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2010-02-23ARM CP15 tls fixPaul Brook1-9/+7
Fix temporary handling in cp15 tls register load/store. Signed-off-by: Paul Brook <paul@codesourcery.com>
2010-02-19target-arm: support thumb exception handlersRabin Vincent1-3/+2
When handling an exception, switch to the correct mode based on the Thumb Exception (TE) bit in the SCTLR. Signed-off-by: Rabin Vincent <rabin@rab.in>
2010-02-19target-arm: implement Thumb-2 exception returnRabin Vincent1-2/+10
Support the "subs pc, lr" Thumb-2 exception return instruction. Signed-off-by: Rabin Vincent <rabin@rab.in> Signed-off-by: Paul Brook <paul@codesourcery.com>
2010-02-19target-arm: fix thumb CPSRabin Vincent1-1/+1
The Thumb CPS currently does not work correctly: CPSID touches more bits than the instruction wants to, and CPSIE does nothing. Fix it by passing the correct mask (the "affect" bits) and value. Signed-off-by: Rabin Vincent <rabin@rab.in>
2010-02-06target-arm: refactor cp15.c13 register accessRiku Voipio2-16/+55
Access the cp15.c13 TLS registers directly with TCG ops instead of with a slow helper. If the the cp15 read/write was not TLS register access, fall back to the cp15 helper. This makes accessing __thread variables in linux-user when apps are compiled with -mtp=cp15 possible. legal cp15 register to acces from linux-user are already checked in cp15_user_ok. While at it, make the cp15.c13 Thread ID registers available only on ARMv6K and newer. Signed-off-by: Riku Voipio <riku.voipio@nokia.com>
2010-01-19kill regs_to_env and env_to_regsPaolo Bonzini1-8/+0
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com> Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
2009-12-24target-arm: fix strexdAurelien Jarno1-1/+1
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2009-11-22ARM atomic ops rewritePaul Brook4-176/+171
Implement ARMv6 atomic ops (ldrex/strex) using the same trick as PPC. Signed-off-by: Paul Brook <paul@codesourcery.com>
2009-11-19ARM Cortex-A9 cpu supportPaul Brook2-1/+36
Basic Cortex-A9 support. Signed-off-by: Paul Brook <paul@codesourcery.com>
2009-11-19ARM FP16 supportPaul Brook4-0/+105
Implement the ARM VFP half precision floating point extensions. Signed-off-by: Paul Brook <paul@codesourcery.com>
2009-10-27target-arm: use native tcg-ops for ror/bic/vornAurelien Jarno3-47/+14
Acked-by: Laurent Desnogues <laurent.desnogues@gmail.com> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2009-10-27target-arm: fix neon shift helper functionsJuha Riihimäki1-12/+14
Current code is broken at least on recent compilers, comparison between signed and unsigned types yield incorrect code and render the neon shift helper functions defunct. This is the third revision of this patch, casting all comparisons with the sizeof operator to signed ssize_t type to force comparisons to be between signed integral types. Signed-off-by: Juha Riihimäki <juha.riihimaki@nokia.com> Acked-by: Laurent Desnogues <laurent.desnogues@gmail.com> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2009-10-27target-arm: fix neon vsri, vshl and vsli opsJuha Riihimäki1-14/+18
Shift by immediate value is incorrectly overwritten by a temporary variable in the processing of NEON vsri, vshl and vsli instructions. This patch has been revised to also include a fix for the special case where the code would previously try to shift an integer value over 31 bits left/right. Signed-off-by: Juha Riihimäki <juha.riihimaki@nokia.com> Acked-by: Laurent Desnogues <laurent.desnogues@gmail.com> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2009-10-27target-arm: allow modifying vfp fpexc en bit onlyJuha Riihimäki2-1/+4
All other bits except for the EN in the VFP FPEXC register are defined as subarchitecture specific and real functionality for any of the other bits has not been implemented in QEMU. However, current code allows modifying all bits in the VFP FPEXC register leading to problems when guest code is writing 1's to the subarchitecture specific bits and checking whether the bits stay up to verify the existence of functionality which in fact does not exist in QEMU. This patch has been revised to include the same behavior change in the gdb register write function. Signed-off-by: Juha Riihimäki <juha.riihimaki@nokia.com> Acked-by: Laurent Desnogues <laurent.desnogues@gmail.com> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2009-10-27target-arm: add support for neon vld1.64/vst1.64 instructionsJuha Riihimäki1-52/+81
Add support for NEON vld1.64 and vst1.64 instructions. This patch is revised to follow more closely the specification and raises undefined exception if 64bit element size is used for vld2/vst2 or vld4/vst4 instructions. Signed-off-by: Juha Riihimäki <juha.riihimaki@nokia.com> Acked-by: Laurent Desnogues <laurent.desnogues@gmail.com> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2009-10-27target-arm: fix neon vshrn/vrshrn opsJuha Riihimäki1-9/+3
In the existing code shift value is clobbered during the pass loop. This patch changes the code so that it stores the intermediate result in the target neon register directly and eliminates the need to use a temporary to hold the intermediate value thus leaving the shift value in the temporary variable intact. This is a new patch in this version of the patch series. Signed-off-by: Juha Riihimäki <juha.riihimaki@nokia.com> Acked-by: Laurent Desnogues <laurent.desnogues@gmail.com> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2009-10-26target-arm: fix incorrect temporary variable freeingJuha Riihimäki1-2/+2
tmp4 and tmp5 temporary variables are allocated using tcg_const_i32 but incorrectly released using dead_tmp which will cause resource leak tracking to report false leaks. Signed-off-by: Juha Riihimäki <juha.riihimaki@nokia.com> Acked-by: Laurent Desnogues <laurent.desnogues@gmail.com> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2009-10-23target-arm: optimize thumb 32-bit multiplyJuha.Riihimaki@nokia.com1-17/+1
Current implementation of thumb mul instruction is implemented as a 32x32->64 multiply which then uses only 32 least significant bits of the result. Replace that with a simple 32x32->32 multiply. Signed-off-by: Juha Riihimäki <juha.riihimaki@nokia.com> Acked-by: Laurent Desnogues <laurent.desnogues@gmail.com> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2009-10-23target-arm: cleanup internal resource leaksJuha Riihimäki1-27/+89
Revised patch for getting rid of tcg temporary variable leaks in target-arm/translate.c. This version also includes the leak patch for gen_set_cpsr macro, now converted as a static inline function, which I sent earlier as a separate patch on top of this patch. Signed-off-by: Juha Riihimäki <juha.riihimaki@nokia.com> Acked-by: Laurent Desnogues <laurent.desnogues@gmail.com> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2009-10-23target-arm: fix sdiv helperAurelien Jarno1-0/+2
(INT32_MIN / -1) triggers an overflow, and the result depends on the host architecture (INT32_MIN on arm, -1 on ppc, SIGFPE on x86). Use a test to output the correct value. Signed-off-by: Aurelien Jarno <aurelien@aurel32.net> Acked-by: Laurent Desnogues <laurent.desnogues@gmail.com>
2009-10-23target-arm: use clz32() instead of a for loopAurelien Jarno1-4/+2
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net> Acked-by: Laurent Desnogues <laurent.desnogues@gmail.com>
2009-10-18target-arm: fix bugs introduced by 1b2b1e547bd912b7d3c4863d0a0f75f6f38330edAurelien Jarno1-5/+7
Use load_reg_var() instead of accessing cpu_R[rn] directly to generate correct code when rn = 15. Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2009-10-18target-arm: fix bugs introduced by 3174f8e91fecf8756e861d1febb049f3c619a2c7Aurelien Jarno1-3/+3
Use load_reg_var() instead of accessing cpu_R[rn] directly to generate correct code when rn = 15. Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2009-10-17target-arm: remove T0 and T1Aurelien Jarno1-2/+0
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2009-10-17target-arm: remove cpu_T for ARM once and for allFilip Navara1-26/+0
Signed-off-by: Filip Navara <filip.navara@gmail.com> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2009-10-17target-arm: convert VFP not to use cpu_TFilip Navara1-28/+22
Signed-off-by: Filip Navara <filip.navara@gmail.com> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2009-10-17target-arm: convert disas_iwmmxt_insn not to use cpu_TFilip Navara1-252/+219
Signed-off-by: Filip Navara <filip.navara@gmail.com> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2009-10-17target-arm: convert disas_dsp_insn not use cpu_TFilip Navara1-39/+20
Signed-off-by: Filip Navara <filip.navara@gmail.com> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2009-10-17target-arm: convert disas_neon_ls_insn not to use cpu_TFilip Navara1-33/+34
Signed-off-by: Filip Navara <filip.navara@gmail.com> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2009-10-17target-arm: convert disas_neon_data_insn and helpers not to use cpu_TFilip Navara1-296/+271
Signed-off-by: Filip Navara <filip.navara@gmail.com> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2009-10-17target-arm: convert rest of disas_arm_insn / disas_thumb2_insn not to use cpu_TFilip Navara1-41/+56
Signed-off-by: Filip Navara <filip.navara@gmail.com> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2009-10-17target-arm: replace thumb usage of cpu_T registers by proper register ↵Filip Navara1-129/+139
allocations The goal is eventually to get rid of all cpu_T register usage and to use just short-lived tmp/tmp2 registers. This patch converts all the places where cpu_T was used in the Thumb code and replaces it with explicit TCG register allocation. Signed-off-by: Filip Navara <filip.navara@gmail.com> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2009-10-17target-arm: fix TANDC and TORC instructionsFilip Navara1-0/+2
Uninitialized register was used instead of proper TCG variable. Signed-off-by: Filip Navara <filip.navara@gmail.com> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2009-10-17target-arm: convert NEON VZIP/VUZP/VTRN helper functions to pure TCGFilip Navara3-73/+142
The neon_trn_u8, neon_trn_u16, neon_unzip_u8, neon_zip_u8 and neon_zip_u16 helpers used fixed registers to return values. This patch replaces that with TCG code, so T0/T1 is no longer directly used by the helper functions. Bugs in the gen_neon_unzip register load code were also fixed. Signed-off-by: Filip Navara <filip.navara@gmail.com> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2009-10-17target-arm: convert gen_lookup_tb not to use cpu_TFilip Navara1-2/+1
Signed-off-by: Filip Navara <filip.navara@gmail.com> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2009-10-17target-arm: get rid of gen_set_psr_T0 and replace it by ↵Filip Navara1-20/+24
gen_set_psr/gen_set_psr_im Signed-off-by: Filip Navara <filip.navara@gmail.com> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2009-10-17target-arm: fix SRS/RFE instructionsFilip Navara1-15/+16
The encoding of 'IA' and 'DB' conditions was swapped. SRS instruction must store banked SPSR instead of CPSR at the specific address. Missing 'return' statement at the end of RFE handling. Fixed write-back code to reference correct registers. From: Hyeonsung Jang <hsjang@ok-labs.com> Signed-off-by: Filip Navara <filip.navara@gmail.com> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2009-10-17target-arm: remove unused gen_movl_T2_reg functionFilip Navara1-5/+0
Signed-off-by: Filip Navara <filip.navara@gmail.com> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2009-10-17target-arm: remove useless line that sets register that is never used againFilip Navara1-1/+0
Signed-off-by: Filip Navara <filip.navara@gmail.com> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2009-10-17target-arm: get rid of temporary variable cacheFilip Navara1-28/+3
The temporary variable cache in no longer need since tcg_temp_free was introduced. Signed-off-by: Filip Navara <filip.navara@gmail.com> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2009-10-17target-arm: use tcg_global_mem_new_i32 to allocate registersFilip Navara1-17/+23
Currently each read/write of ARM register involves a LD/ST TCG operation. This patch uses TCG memory-backed registers to represent the ARM register set. With memory-backed registers the LD/ST operations are transparently generated by TCG and host registers could be used to optimize the generated code. Signed-off-by: Filip Navara <filip.navara@gmail.com> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
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