index
:
sdk/emulator/qemu
1.0_post
2.0alpha
features/brillcodec_2i
features/camera
features/cnp
features/dr
features/qt_dr
features/smp
features/virtio-9p
features/vmodem
glesv3
master
opensrc_p2.3
opensrc_p2.3.1
opensrc_p2.3.2
opensrc_p2.4
opensrc_p3.0
opensrc_p4.0
sandbox/byungchul.so/tizen
sandbox/elebideau/tizen
sandbox/mmajewski2/maru-virgl-rendering-wip
sandbox/mmajewski2/standalone-virgl-wip
sandbox/pcoval/tizen
spin
tizen
tizen_2.0
tizen_2.1
tizen_2.2
tizen_3.0.m14.4_ivi
tizen_p2.3
tizen_p2.3.1
tizen_qemu_1.6
tizen_qemu_1.7
tizen_qemu_2.0
tizen_qemu_5.0.1
tizen_studio_1.2_p2.3
tizen_studio_1.2_p2.3.1
tizen_studio_1.2_p2.3.2
tizen_studio_1.2_p2.4
tizen_studio_1.2_p3.0
tizen_studio_1.3_p2.3
tizen_studio_1.3_p2.3.1
tizen_studio_1.3_p2.3.2
tizen_studio_1.3_p2.4
tizen_studio_1.3_p3.0
tizen_studio_2.0_p2.3
tizen_studio_2.0_p2.3.1
tizen_studio_2.0_p2.3.2
tizen_studio_2.0_p2.4
tizen_studio_2.0_p3.0
tizen_studio_2.0_p4.0
tizen_studio_2.0_p5.0
tizen_studio_3.0_p2.3
tizen_studio_3.0_p2.3.1
tizen_studio_3.0_p2.3.2
tizen_studio_3.0_p2.4
tizen_studio_3.0_p3.0
tizen_studio_3.0_p4.0
tizen_studio_3.0_p5.0
tizen_studio_3.5_p2.3
tizen_studio_3.5_p2.3.1
tizen_studio_3.5_p2.3.2
tizen_studio_3.5_p2.4
tizen_studio_3.5_p3.0
tizen_studio_3.5_p4.0
tizen_studio_3.5_p5.0
tizen_studio_3.5_p5.5
tizen_studio_4.0_p2.3
tizen_studio_4.0_p2.3.1
tizen_studio_4.0_p2.3.2
tizen_studio_4.0_p2.4
tizen_studio_4.0_p3.0
tizen_studio_4.0_p4.0
tizen_studio_4.0_p5.0
tizen_studio_4.0_p5.5
tizen_studio_4.0_p6.0
tizen_studio_4.5_p6.5
tizen_studio_5.0_p7.0
tizen_studio_5.5_p7.5
tizen_studio_5.5_p8.0
tizen_studio_6.0_p9.0
tizen_studio_p2.3
tizen_studio_p2.3.1
tizen_studio_p2.3.2
tizen_studio_p2.4
tizen_studio_p3.0
tizen_studio_p4.0
works/arg_renewal
Domain: SDK / Emulator;
summary
refs
log
tree
commit
diff
log msg
author
committer
range
path:
root
/
target-arm
Age
Commit message (
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)
Author
Files
Lines
2015-09-15
target-arm: Use new revbit functions
Richard Henderson
2
-25
/
+2
2015-09-14
target-arm: Add VMPIDR_EL2
Edgar E. Iglesias
2
-2
/
+25
2015-09-14
target-arm: Break out mpidr_read_val()
Edgar E. Iglesias
1
-1
/
+6
2015-09-14
target-arm: Add VPIDR_EL2
Edgar E. Iglesias
2
-1
/
+42
2015-09-14
target-arm: Suppress EPD for S2, EL2 and EL3 translations
Edgar E. Iglesias
1
-2
/
+4
2015-09-14
target-arm: Suppress TBI for S2 translations
Edgar E. Iglesias
1
-1
/
+3
2015-09-14
target-arm: Add VTTBR_EL2
Edgar E. Iglesias
2
-2
/
+33
2015-09-14
target-arm: Add VTCR_EL2
Edgar E. Iglesias
2
-2
/
+42
2015-09-14
target-arm: Use tcg_gen_extrh_i64_i32
Richard Henderson
1
-25
/
+9
2015-09-14
target-arm: Recognize ROR
Richard Henderson
1
-12
/
+21
2015-09-14
target-arm: Eliminate unnecessary zero-extend in disas_bitfield
Richard Henderson
1
-1
/
+5
2015-09-14
target-arm: Recognize UXTB, UXTH, LSR, LSL
Richard Henderson
1
-0
/
+17
2015-09-14
target-arm: Recognize SXTB, SXTH, SXTW, ASR
Richard Henderson
1
-1
/
+23
2015-09-14
target-arm: Implement fcsel with movcond
Richard Henderson
1
-28
/
+17
2015-09-14
target-arm: Implement ccmp branchless
Richard Henderson
1
-16
/
+58
2015-09-14
target-arm: Use setcond and movcond for csel
Richard Henderson
1
-36
/
+49
2015-09-14
target-arm: Handle always condition codes within arm_test_cc
Richard Henderson
1
-0
/
+9
2015-09-14
target-arm: Introduce DisasCompare
Richard Henderson
2
-46
/
+78
2015-09-14
target-arm: Share all common TCG temporaries
Richard Henderson
3
-27
/
+13
2015-09-11
tlb: Add "ifetch" argument to cpu_mmu_index()
Benjamin Herrenschmidt
2
-4
/
+4
2015-09-11
typofixes - v4
Veres Lajos
1
-2
/
+2
2015-09-11
maint: remove / fix many doubled words
Daniel P. Berrange
3
-4
/
+4
2015-09-08
target-arm: Add AArch64 access to PAR_EL1
Edgar E. Iglesias
1
-0
/
+6
2015-09-08
target-arm: Correct opc1 for AT_S12Exx
Edgar E. Iglesias
1
-4
/
+4
2015-09-08
target-arm: Log the target EL when taking exceptions
Edgar E. Iglesias
1
-1
/
+2
2015-09-08
target-arm: Fix default_exception_el() function for the case when EL3 is not ...
Sergey Sorokin
3
-4
/
+13
2015-09-07
target-arm: Refactor CPU affinity handling
Pavel Fedin
4
-5
/
+16
2015-09-07
target-arm: Fix arm_excp_unmasked() function
Sergey Sorokin
1
-3
/
+3
2015-09-07
target-arm: Fix AArch32:AArch64 general-purpose register mapping
Sergey Sorokin
1
-32
/
+32
2015-09-07
arm: Remove hw_error() usages.
Peter Crosthwaite
2
-3
/
+3
2015-09-07
arm: cpu: assert() on no-EL2 virt IRQ error condition.
Peter Crosthwaite
1
-4
/
+1
2015-09-07
target-arm: Wire up HLT 0xf000 as the A64 semihosting instruction
Peter Maydell
4
-2
/
+31
2015-09-07
target-arm/arm-semi.c: SYS_EXIT on A64 takes a parameter block
Peter Maydell
1
-3
/
+18
2015-09-07
target-arm/arm-semi.c: Implement A64 specific SyncCacheRange call
Peter Maydell
1
-0
/
+10
2015-09-07
target-arm/arm-semi.c: Support widening APIs to 64 bits
Peter Maydell
2
-13
/
+58
2015-09-07
target-arm/arm-semi.c: Factor out repeated 'return env->regs[0]'
Peter Maydell
1
-32
/
+47
2015-09-07
target-arm: Improve semihosting debug prints
Christopher Covington
1
-3
/
+9
2015-09-07
target-arm/arm-semi.c: Fix broken SYS_WRITE0 via gdb
Peter Maydell
1
-1
/
+1
2015-08-25
target-arm: Implement AArch64 TLBI operations on IPAs
Peter Maydell
1
-0
/
+55
2015-08-25
target-arm: Implement missing EL3 TLB invalidate operations
Peter Maydell
1
-0
/
+76
2015-08-25
target-arm: Implement missing EL2 TLBI operations
Peter Maydell
1
-0
/
+22
2015-08-25
target-arm: Restrict AArch64 TLB flushes to the MMU indexes they must touch
Peter Maydell
1
-43
/
+129
2015-08-25
target-arm: Move TLBI ALLE1/ALLE1IS definitions into numeric order
Peter Maydell
1
-8
/
+8
2015-08-25
target-arm: Implement AArch32 ATS1H* operations
Peter Maydell
1
-0
/
+22
2015-08-25
target-arm: Enable the AArch32 ATS12NSO ops
Peter Maydell
1
-5
/
+11
2015-08-25
target-arm: Add CP_ACCESS_TRAP_UNCATEGORIZED_EL2, 3
Peter Maydell
2
-0
/
+11
2015-08-25
target-arm: Wire up AArch64 EL2 and EL3 address translation ops
Peter Maydell
1
-2
/
+41
2015-08-25
target-arm: there is no TTBR1 for 32-bit EL2 stage 1 translations
Peter Maydell
1
-0
/
+5
2015-08-25
target-arm: Implement missing ACTLR registers
Peter Maydell
1
-6
/
+15
2015-08-25
target-arm: Implement missing AFSR registers
Peter Maydell
1
-0
/
+24
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