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2015-08-25target-arm: Implement AArch64 TLBI operations on IPAsPeter Maydell1-0/+55
2015-08-25target-arm: Implement missing EL3 TLB invalidate operationsPeter Maydell1-0/+76
2015-08-25target-arm: Implement missing EL2 TLBI operationsPeter Maydell1-0/+22
2015-08-25target-arm: Restrict AArch64 TLB flushes to the MMU indexes they must touchPeter Maydell1-43/+129
2015-08-25target-arm: Move TLBI ALLE1/ALLE1IS definitions into numeric orderPeter Maydell1-8/+8
2015-08-25target-arm: Implement AArch32 ATS1H* operationsPeter Maydell1-0/+22
2015-08-25target-arm: Enable the AArch32 ATS12NSO opsPeter Maydell1-5/+11
2015-08-25target-arm: Add CP_ACCESS_TRAP_UNCATEGORIZED_EL2, 3Peter Maydell2-0/+11
2015-08-25target-arm: Wire up AArch64 EL2 and EL3 address translation opsPeter Maydell1-2/+41
2015-08-25target-arm: there is no TTBR1 for 32-bit EL2 stage 1 translationsPeter Maydell1-0/+5
2015-08-25target-arm: Implement missing ACTLR registersPeter Maydell1-6/+15
2015-08-25target-arm: Implement missing AFSR registersPeter Maydell1-0/+24
2015-08-25target-arm: Implement missing AMAIR registersPeter Maydell1-0/+21
2015-08-25target-arm: Add missing MAIR_EL3 and TPIDR_EL3 registersPeter Maydell1-0/+8
2015-08-24tcg: Remove tcg_gen_trunc_i64_i32Richard Henderson2-53/+53
2015-08-13target-arm: Add AArch32 banked register access to secure physical timerPeter Maydell1-0/+27
2015-08-13target-arm: Add the AArch64 view of the Secure physical timerPeter Maydell4-1/+92
2015-08-13target-arm: Add debug check for mismatched cpreg resetsPeter Maydell3-1/+27
2015-08-13Introduce gic_class_name() instead of repeating conditionPavel Fedin1-0/+5
2015-08-13target-arm: Add the Hypervisor timerEdgar E. Iglesias4-1/+73
2015-08-13target-arm: Pass timeridx as argument to various timer functionsEdgar E. Iglesias1-22/+77
2015-08-13target-arm: Rename and move gt_cnt_resetEdgar E. Iglesias1-7/+5
2015-08-13target-arm: Add CNTHCTL_EL2Edgar E. Iglesias2-2/+32
2015-08-13target-arm: Add CNTVOFF_EL2Edgar E. Iglesias2-6/+42
2015-07-21target-arm: kvm: Differentiate registers based on write-back levelsChristoffer Dall6-6/+76
2015-07-15target-arm: Fix broken SCTLR_EL3 resetPeter Maydell1-0/+1
2015-07-09disas: arm: QOMify target specific disas setupPeter Crosthwaite1-0/+35
2015-07-09cpu-exec: Purge all uses of ENV_GET_CPU()Peter Crosthwaite1-1/+1
2015-07-09cpu: Change cpu_exec_init() arg to cpu, not envPeter Crosthwaite1-1/+1
2015-07-09cpu: Add Error argument to cpu_exec_init()Bharata B Rao1-1/+1
2015-07-07crypto: move built-in AES implementation into crypto/Daniel P. Berrange1-1/+1
2015-07-06target-arm: Implement YIELD insn to yield in ARM and Thumb translatorsPeter Maydell1-0/+7
2015-07-06target-arm: Split DISAS_YIELD from DISAS_WFEPeter Maydell4-3/+23
2015-07-06target-arm: fix write helper for TLBI ALLE1ISSergey Fedorov1-1/+1
2015-06-26target-arm: A64: Print ELR when taking exceptionsSoren Brinkmann1-0/+2
2015-06-26target-arm: default empty semihosting cmdlineLiviu Ionescu1-2/+9
2015-06-22Include qapi/qmp/qerror.h exactly where neededMarkus Armbruster1-1/+0
2015-06-22disas: Remove uses of CPU envPeter Crosthwaite2-2/+2
2015-06-19semihosting: add --semihosting-config arg sub-argumentLeon Alrae1-7/+3
2015-06-19semihosting: create SemihostingConfig structure and semihost.hLeon Alrae1-3/+4
2015-06-19target-arm: Add support for Cortex-R5Peter Crosthwaite1-0/+38
2015-06-19target-arm: Implement PMSAv7 MPUPeter Crosthwaite2-1/+174
2015-06-19target-arm: Add registers for PMSAv7Peter Crosthwaite4-7/+133
2015-06-19target-arm/helper.c: define MPUIR registerPeter Crosthwaite3-0/+30
2015-06-19target-arm: Do not reset sysregs marked as ALIASSergey Fedorov3-22/+12
2015-06-19target-arm: Add the Cortex-M4 CPUAurelio C. Remonda1-0/+11
2015-06-15target-arm: Correct "preferred return address" for cpreg access exceptionsPeter Maydell1-1/+1
2015-06-15arm: helper: rename get_phys_addr_mpuPeter Crosthwaite1-5/+5
2015-06-15arm: Add has-mpu propertyPeter Crosthwaite2-0/+16
2015-06-15arm: Implement uniprocessor with MP configPeter Crosthwaite2-2/+7
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