index
:
sdk/emulator/qemu
1.0_post
2.0alpha
features/brillcodec_2i
features/camera
features/cnp
features/dr
features/qt_dr
features/smp
features/virtio-9p
features/vmodem
glesv3
master
opensrc_p2.3
opensrc_p2.3.1
opensrc_p2.3.2
opensrc_p2.4
opensrc_p3.0
opensrc_p4.0
sandbox/byungchul.so/tizen
sandbox/elebideau/tizen
sandbox/mmajewski2/maru-virgl-rendering-wip
sandbox/mmajewski2/standalone-virgl-wip
sandbox/pcoval/tizen
spin
tizen
tizen_2.0
tizen_2.1
tizen_2.2
tizen_3.0.m14.4_ivi
tizen_p2.3
tizen_p2.3.1
tizen_qemu_1.6
tizen_qemu_1.7
tizen_qemu_2.0
tizen_qemu_5.0.1
tizen_studio_1.2_p2.3
tizen_studio_1.2_p2.3.1
tizen_studio_1.2_p2.3.2
tizen_studio_1.2_p2.4
tizen_studio_1.2_p3.0
tizen_studio_1.3_p2.3
tizen_studio_1.3_p2.3.1
tizen_studio_1.3_p2.3.2
tizen_studio_1.3_p2.4
tizen_studio_1.3_p3.0
tizen_studio_2.0_p2.3
tizen_studio_2.0_p2.3.1
tizen_studio_2.0_p2.3.2
tizen_studio_2.0_p2.4
tizen_studio_2.0_p3.0
tizen_studio_2.0_p4.0
tizen_studio_2.0_p5.0
tizen_studio_3.0_p2.3
tizen_studio_3.0_p2.3.1
tizen_studio_3.0_p2.3.2
tizen_studio_3.0_p2.4
tizen_studio_3.0_p3.0
tizen_studio_3.0_p4.0
tizen_studio_3.0_p5.0
tizen_studio_3.5_p2.3
tizen_studio_3.5_p2.3.1
tizen_studio_3.5_p2.3.2
tizen_studio_3.5_p2.4
tizen_studio_3.5_p3.0
tizen_studio_3.5_p4.0
tizen_studio_3.5_p5.0
tizen_studio_3.5_p5.5
tizen_studio_4.0_p2.3
tizen_studio_4.0_p2.3.1
tizen_studio_4.0_p2.3.2
tizen_studio_4.0_p2.4
tizen_studio_4.0_p3.0
tizen_studio_4.0_p4.0
tizen_studio_4.0_p5.0
tizen_studio_4.0_p5.5
tizen_studio_4.0_p6.0
tizen_studio_4.5_p6.5
tizen_studio_5.0_p7.0
tizen_studio_5.5_p7.5
tizen_studio_5.5_p8.0
tizen_studio_6.0_p9.0
tizen_studio_p2.3
tizen_studio_p2.3.1
tizen_studio_p2.3.2
tizen_studio_p2.4
tizen_studio_p3.0
tizen_studio_p4.0
works/arg_renewal
Domain: SDK / Emulator;
summary
refs
log
tree
commit
diff
log msg
author
committer
range
path:
root
/
target-arm
Age
Commit message (
Expand
)
Author
Files
Lines
2016-03-16
target-arm: Fix translation level on early translation faults
Sergey Sorokin
1
-10
/
+12
2016-03-16
target-arm: Implement MRS (banked) and MSR (banked) instructions
Peter Maydell
3
-3
/
+366
2016-03-04
target-arm: Only trap SRS from S-EL1 if specified mode is MON
Ralf-Philipp Weinmann
1
-1
/
+2
2016-03-04
target-arm: implement BE32 mode in system emulation
Paolo Bonzini
2
-18
/
+73
2016-03-04
target-arm: implement setend
Paolo Bonzini
3
-8
/
+12
2016-03-04
target-arm: introduce tbflag for endianness
Peter Crosthwaite
3
-2
/
+9
2016-03-04
target-arm: a64: Add endianness support
Peter Crosthwaite
1
-19
/
+30
2016-03-04
target-arm: introduce disas flag for endianness
Paolo Bonzini
3
-15
/
+26
2016-03-04
target-arm: pass DisasContext to gen_aa32_ld*/st*
Paolo Bonzini
1
-128
/
+142
2016-03-04
target-arm: implement SCTLR.EE
Peter Crosthwaite
1
-2
/
+21
2016-03-04
linux-user: arm: handle CPSR.E correctly in strex emulation
Paolo Bonzini
1
-0
/
+11
2016-03-04
arm: cpu: handle BE32 user-mode as BE
Peter Crosthwaite
1
-1
/
+16
2016-03-04
target-arm: cpu: Move cpu_is_big_endian to header
Peter Crosthwaite
2
-16
/
+22
2016-03-04
target-arm: implement SCTLR.B, drop bswap_code
Paolo Bonzini
7
-29
/
+60
2016-03-04
target-arm: Correct handling of writes to CPSR mode bits from gdb in usermode
Peter Maydell
1
-2
/
+9
2016-03-01
tcg: Add type for vCPU pointers
LluĂs Vilanova
2
-2
/
+2
2016-02-26
target-arm: Make reserved ranges in ID_AA64* spaces RAZ, not UNDEF
Peter Maydell
2
-7
/
+122
2016-02-26
target-arm: Mark CNTHP_TVAL_EL2 as ARM_CP_NO_RAW
Edgar E. Iglesias
1
-1
/
+1
2016-02-26
target-arm: Implement MDCR_EL3.TPM and MDCR_EL2.TPM traps
Peter Maydell
1
-7
/
+36
2016-02-26
target-arm: Fix handling of SDCR for 32-bit code
Peter Maydell
2
-8
/
+19
2016-02-26
target-arm: Make Monitor->NS PL1 mode changes illegal if HCR.TGE is 1
Peter Maydell
1
-0
/
+10
2016-02-26
target-arm: Make mode switches from Hyp via CPS and MRS illegal
Peter Maydell
1
-2
/
+10
2016-02-26
target-arm: In v8, make illegal AArch32 mode changes set PSTATE.IL
Peter Maydell
1
-3
/
+12
2016-02-26
target-arm: Forbid mode switch to Mon from Secure EL1
Peter Maydell
1
-1
/
+1
2016-02-26
target-arm: Add Hyp mode checks to bad_mode_switch()
Peter Maydell
1
-0
/
+3
2016-02-26
target-arm: Add comment about not implementing NSACR.RFR
Peter Maydell
1
-0
/
+3
2016-02-26
target-arm: In cpsr_write() ignore mode switches from User mode
Peter Maydell
1
-0
/
+1
2016-02-26
target-arm: Raw CPSR writes should skip checks and bank switching
Peter Maydell
4
-6
/
+7
2016-02-26
target-arm: Add write_type argument to cpsr_write()
Peter Maydell
7
-10
/
+20
2016-02-26
target-arm: Give CPSR setting on 32-bit exception return its own helper
Peter Maydell
3
-3
/
+10
2016-02-23
all: Clean up includes
Peter Maydell
2
-2
/
+0
2016-02-18
target-arm: Add PMUSERENR_EL0 register
Alistair Francis
1
-0
/
+6
2016-02-18
target-arm: Add the pmovsclr_el0 and pmintenclr_el1 registers
Alistair Francis
1
-0
/
+12
2016-02-18
target-arm: Add the pmceid0 and pmceid1 registers
Alistair Francis
4
-0
/
+22
2016-02-18
target-arm: UNDEF in the UNPREDICTABLE SRS-from-System case
Peter Maydell
2
-4
/
+13
2016-02-18
target-arm: Combine user-only and softmmu get/set_r13_banked()
Peter Maydell
1
-19
/
+0
2016-02-18
target-arm: Move bank_number() into internals.h
Peter Maydell
2
-26
/
+25
2016-02-18
target-arm: Move get/set_r13_banked() to op_helper.c
Peter Maydell
2
-33
/
+37
2016-02-18
target-arm: Clean up trap/undef handling of SRS
Peter Maydell
1
-5
/
+61
2016-02-18
target-arm: Report correct syndrome for FPEXC32_EL2 traps
Peter Maydell
3
-2
/
+20
2016-02-18
target-arm: Implement MDCR_EL3.TDA and MDCR_EL2.TDA traps
Peter Maydell
1
-9
/
+30
2016-02-18
target-arm: Implement MDCR_EL2.TDRA traps
Peter Maydell
1
-3
/
+24
2016-02-18
target-arm: Implement MDCR_EL3.TDOSA and MDCR_EL2.TDOSA traps
Peter Maydell
2
-1
/
+34
2016-02-18
target-arm: Fix handling of SCR.SMD
Peter Maydell
1
-5
/
+7
2016-02-18
target-arm: correct CNTFRQ access rights
Peter Maydell
2
-3
/
+38
2016-02-11
target-arm: Implement checking of fired watchpoint
Sergey Fedorov
3
-14
/
+25
2016-02-11
target-arm: Fix IL bit reported for Thumb VFP and Neon traps
Peter Maydell
1
-3
/
+3
2016-02-11
target-arm: Fix IL bit reported for Thumb coprocessor traps
Peter Maydell
1
-4
/
+4
2016-02-11
target-arm: Correct misleading 'is_thumb' syn_* parameter names
Peter Maydell
1
-14
/
+14
2016-02-11
target-arm: Enable EL3 for Cortex-A53 and Cortex-A57
Peter Maydell
1
-0
/
+2
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