| Age | Commit message (Expand) | Author | Files | Lines |
|---|
| 2014-12-11 | target-arm: add secure state bit to CPREG hash | Peter Maydell | 1 | -5/+9 |
| 2014-12-11 | target-arm: add non-secure Translation Block flag | Sergey Fedorov | 1 | -0/+1 |
| 2014-11-04 | target-arm/translate.c: Don't pass CPUARMState * to disas_arm_insn() | Peter Maydell | 1 | -6/+5 |
| 2014-11-04 | target-arm/translate.c: Don't pass CPUARMState around in the decoder | Peter Maydell | 1 | -44/+50 |
| 2014-11-04 | target-arm/translate.c: Don't use IS_M() | Peter Maydell | 1 | -8/+11 |
| 2014-11-04 | target-arm/translate.c: Use arm_dc_feature() rather than arm_feature() | Peter Maydell | 1 | -60/+80 |
| 2014-11-04 | target-arm/translate.c: Use arm_dc_feature() in ENABLE_ARCH_ macros | Peter Maydell | 1 | -8/+8 |
| 2014-10-24 | target-arm: rename arm_current_pl to arm_current_el | Greg Bellows | 1 | -2/+2 |
| 2014-10-24 | target-arm: correctly UNDEF writes to FPINST/FPINST2 from EL0 | Peter Maydell | 1 | -0/+3 |
| 2014-10-24 | target-arm: Add support for A32 and T32 HVC and SMC insns | Peter Maydell | 1 | -11/+92 |
| 2014-09-29 | target-arm: Don't handle c15_cpar changes via tb_flush() | Peter Maydell | 1 | -19/+21 |
| 2014-08-19 | target-arm: Implement ARMv8 single-stepping for AArch32 code | Peter Maydell | 1 | -2/+74 |
| 2014-08-19 | target-arm: Don't allow AArch32 to access RES0 CPSR bits | Peter Maydell | 1 | -6/+7 |
| 2014-08-12 | trace: [tcg] Include TCG-tracing header on all targets | Lluís Vilanova | 1 | -0/+3 |
| 2014-06-09 | target-arm: Delete unused iwmmxt_msadb helper | Peter Maydell | 1 | -2/+0 |
| 2014-06-09 | target-arm: A32/T32: Mask CRC value in calling code, not helper | Peter Maydell | 1 | -0/+10 |
| 2014-06-09 | target-arm: add support for v8 VMULL.P64 instruction | Peter Maydell | 1 | -1/+25 |
| 2014-06-09 | target-arm: Allow 3reg_wide undefreq to encode more bad size options | Peter Maydell | 1 | -12/+12 |
| 2014-06-09 | target-arm: add support for v8 SHA1 and SHA256 instructions | Ard Biesheuvel | 1 | -0/+84 |
| 2014-06-05 | target-arm: move arm_*_code to a separate file | Paolo Bonzini | 1 | -0/+1 |
| 2014-05-28 | tcg: Invert the inclusion of helper.h | Richard Henderson | 1 | -3/+2 |
| 2014-05-27 | target-arm: Add SPSR entries for EL2/HYP and EL3/MON | Edgar E. Iglesias | 1 | -2/+2 |
| 2014-05-27 | target-arm: A32: Use get_mem_index for load/stores | Edgar E. Iglesias | 1 | -106/+106 |
| 2014-05-27 | target-arm/translate.c: Use get_mem_index() for SRS memory accesses | Peter Maydell | 1 | -2/+2 |
| 2014-05-27 | target-arm/translate.c: Clean up mmu index handling for ldrt/strt | Peter Maydell | 1 | -12/+17 |
| 2014-04-17 | arm: translate.c: Fix smlald Instruction | Peter Crosthwaite | 1 | -11/+23 |
| 2014-04-17 | target-arm: Dump 32-bit CPU state if 64 bit CPU is in AArch32 | Peter Maydell | 1 | -0/+5 |
| 2014-04-17 | target-arm: Implement ARMv8 MVFR registers | Peter Maydell | 1 | -2/+8 |
| 2014-04-17 | target-arm: Fix VFP enables for AArch32 EL0 under AArch64 EL1 | Peter Maydell | 1 | -0/+31 |
| 2014-04-17 | target-arm: Add support for generating exceptions with syndrome information | Peter Maydell | 1 | -38/+65 |
| 2014-04-17 | target-arm: Provide correct syndrome information for cpreg access traps | Peter Maydell | 1 | -1/+44 |
| 2014-04-17 | target-arm: Split out private-to-target functions into internals.h | Peter Maydell | 1 | -0/+1 |
| 2014-03-17 | target-arm: A64: Add [UF]RSQRTE (reciprocal root estimate) | Alex Bennée | 1 | -2/+10 |
| 2014-03-17 | target-arm: A64: Implement AdvSIMD reciprocal estimate insns URECPE, FRECPE | Alex Bennée | 1 | -2/+10 |
| 2014-03-17 | target-arm: A64: Implement PMULL instruction | Peter Maydell | 1 | -0/+1 |
| 2014-03-13 | exec: Change cpu_abort() argument to CPUState | Andreas Färber | 1 | -1/+1 |
| 2014-03-13 | cpu: Move breakpoints field from CPU_COMMON to CPUState | Andreas Färber | 1 | -2/+2 |
| 2014-03-10 | target-arm: Implement WFE as a yield operation | Peter Maydell | 1 | -0/+6 |
| 2014-02-26 | target-arm: Add support for AArch32 ARMv8 CRC32 instructions | Will Newton | 1 | -0/+56 |
| 2014-02-20 | target-arm: Remove unnecessary code now read/write fns can't fail | Peter Maydell | 1 | -4/+0 |
| 2014-02-20 | target-arm: Split cpreg access checks out from read/write functions | Peter Maydell | 1 | -0/+11 |
| 2014-02-20 | target-arm: Log bad system register accesses with LOG_UNIMP | Peter Maydell | 1 | -0/+13 |
| 2014-02-08 | target-arm: Add support for AArch32 64bit VCVTB and VCVTT | Will Newton | 1 | -22/+61 |
| 2014-01-31 | target-arm: Add AArch32 SIMD VCVTA, VCVTN, VCVTP and VCVTM | Will Newton | 1 | -1/+52 |
| 2014-01-31 | target-arm: Add AArch32 FP VCVTA, VCVTN, VCVTP and VCVTM | Will Newton | 1 | -0/+61 |
| 2014-01-31 | target-arm: Add AArch32 SIMD VRINTA, VRINTN, VRINTP, VRINTM, VRINTZ | Will Newton | 1 | -1/+39 |
| 2014-01-31 | target-arm: Add support for AArch32 SIMD VRINTX | Will Newton | 1 | -1/+10 |
| 2014-01-31 | target-arm: Add support for AArch32 FP VRINTX | Will Newton | 1 | -0/+11 |
| 2014-01-31 | target-arm: Add support for AArch32 FP VRINTZ | Will Newton | 1 | -0/+16 |
| 2014-01-31 | target-arm: Add support for AArch32 FP VRINTR | Will Newton | 1 | -0/+11 |
