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path: root/target-arm/translate.c
AgeCommit message (Expand)AuthorFilesLines
2016-05-19cpu: move exec-all.h inclusion out of cpu.hPaolo Bonzini1-0/+1
2016-05-12tcg: Allow goto_tb to any target PC in user modeSergey Fedorov1-6/+12
2016-05-12tcg: Clean up direct block chaining safety checksSergey Fedorov1-1/+2
2016-03-22target-arm: dfilter support for in_asmAlex Bennée1-1/+2
2016-03-16target-arm: Implement MRS (banked) and MSR (banked) instructionsPeter Maydell1-3/+243
2016-03-04target-arm: Only trap SRS from S-EL1 if specified mode is MONRalf-Philipp Weinmann1-1/+2
2016-03-04target-arm: implement BE32 mode in system emulationPaolo Bonzini1-15/+71
2016-03-04target-arm: implement setendPaolo Bonzini1-8/+6
2016-03-04target-arm: introduce tbflag for endiannessPeter Crosthwaite1-1/+1
2016-03-04target-arm: introduce disas flag for endiannessPaolo Bonzini1-15/+24
2016-03-04target-arm: pass DisasContext to gen_aa32_ld*/st*Paolo Bonzini1-128/+142
2016-03-04target-arm: implement SCTLR.B, drop bswap_codePaolo Bonzini1-8/+8
2016-03-01tcg: Add type for vCPU pointersLluís Vilanova1-1/+1
2016-02-26target-arm: Give CPSR setting on 32-bit exception return its own helperPeter Maydell1-3/+3
2016-02-18target-arm: UNDEF in the UNPREDICTABLE SRS-from-System casePeter Maydell1-4/+5
2016-02-18target-arm: Clean up trap/undef handling of SRSPeter Maydell1-5/+61
2016-02-11target-arm: Fix IL bit reported for Thumb VFP and Neon trapsPeter Maydell1-3/+3
2016-02-11target-arm: Fix IL bit reported for Thumb coprocessor trapsPeter Maydell1-4/+4
2016-02-11target-arm: Add isread parameter to CPAccessFnsPeter Maydell1-2/+5
2016-02-09tcg: Change tcg_global_mem_new_* to take a TCGv_ptrRichard Henderson1-9/+9
2016-02-09tcg: Remove lingering references to gen_opc_bufRichard Henderson1-2/+1
2016-02-03log: do not unnecessarily include qom/cpu.hPaolo Bonzini1-0/+1
2016-01-18target-arm: Clean up includesPeter Maydell1-5/+1
2015-12-17target-arm: Fix and improve AA32 singlestep translation completion codeSergey Fedorov1-34/+31
2015-12-17target-arm: raise exception on misaligned LDREX operandsAndrew Baumann1-4/+7
2015-11-19target-arm: Update condexec before arch BP check in AA32 translationSergey Fedorov1-0/+1
2015-11-19target-arm: Update condexec before CP access check in AA32 translationSergey Fedorov1-0/+1
2015-11-12target-arm: Update PC before calling gen_helper_check_breakpoints()Sergey Fedorov1-0/+1
2015-11-10target-arm: Clean up DISAS_UPDATE usage in AArch32 translation codeSergey Fedorov1-11/+14
2015-11-03target-arm: Report S/NS status in the CPU debug logsPeter Maydell1-1/+11
2015-10-28target-*: Advance pc after recognizing a breakpointRichard Henderson1-2/+5
2015-10-27target-arm/translate.c: Handle non-executable page-straddling Thumb insnsPeter Maydell1-1/+44
2015-10-16target-arm: Fix CPU breakpoint handlingSergey Fedorov1-5/+14
2015-10-16target-arm: Break the TB after ISB to execute self-modified code correctlySergey Sorokin1-2/+15
2015-10-07tcg: Remove gen_intermediate_code_pcRichard Henderson1-45/+9
2015-10-07tcg: Pass data argument to restore_state_to_opcRichard Henderson1-4/+5
2015-10-07tcg: Add TCG_MAX_INSNSRichard Henderson1-1/+5
2015-10-07target-arm: Add condexec state to insn_startRichard Henderson1-1/+2
2015-10-07target-*: Introduce and use cpu_breakpoint_testRichard Henderson1-15/+16
2015-10-07target-*: Increment num_insns immediately after tcg_gen_insn_startRichard Henderson1-3/+4
2015-10-07target-*: Unconditionally emit tcg_gen_insn_startRichard Henderson1-4/+1
2015-10-07tcg: Rename debug_insn_start to insn_startRichard Henderson1-1/+1
2015-09-14target-arm: Handle always condition codes within arm_test_ccRichard Henderson1-0/+9
2015-09-14target-arm: Introduce DisasCompareRichard Henderson1-46/+69
2015-09-14target-arm: Share all common TCG temporariesRichard Henderson1-5/+5
2015-09-11maint: remove / fix many doubled wordsDaniel P. Berrange1-1/+1
2015-09-08target-arm: Fix default_exception_el() function for the case when EL3 is not ...Sergey Sorokin1-1/+5
2015-08-24tcg: Remove tcg_gen_trunc_i64_i32Richard Henderson1-23/+23
2015-07-06target-arm: Implement YIELD insn to yield in ARM and Thumb translatorsPeter Maydell1-0/+7
2015-06-22disas: Remove uses of CPU envPeter Crosthwaite1-1/+1
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