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path: root/target-arm/helper.c
AgeCommit message (Expand)AuthorFilesLines
2016-05-19cpu: move exec-all.h inclusion out of cpu.hPaolo Bonzini1-0/+1
2016-05-19arm: move arm_log_exception into .c filePaolo Bonzini1-0/+15
2016-05-12target-arm: Avoid unnecessary TLB flush on TCR_EL2, TCR_EL3 writesPeter Maydell1-4/+8
2016-05-12target-arm: Fix descriptor address masking in ARM address translationSergey Sorokin1-18/+11
2016-05-12target-arm: Stage 2 permission fault was fixed in AArch32 stateSergey Sorokin1-1/+3
2016-04-04target-arm: Make the 64-bit version of VTCR do the migrationPeter Maydell1-1/+5
2016-04-04target-arm: Remove incorrect ALIAS tags from ESR_EL2 and ESR_EL3Peter Maydell1-2/+0
2016-04-04target-arm: Correctly reset SCTLR_EL3 for 64-bit CPUsPeter Maydell1-10/+13
2016-03-16target-arm: Fix translation level on early translation faultsSergey Sorokin1-10/+12
2016-03-04target-arm: implement SCTLR.EEPeter Crosthwaite1-2/+21
2016-03-04target-arm: implement SCTLR.B, drop bswap_codePaolo Bonzini1-4/+4
2016-03-04target-arm: Correct handling of writes to CPSR mode bits from gdb in usermodePeter Maydell1-2/+9
2016-02-26target-arm: Make reserved ranges in ID_AA64* spaces RAZ, not UNDEFPeter Maydell1-7/+121
2016-02-26target-arm: Mark CNTHP_TVAL_EL2 as ARM_CP_NO_RAWEdgar E. Iglesias1-1/+1
2016-02-26target-arm: Implement MDCR_EL3.TPM and MDCR_EL2.TPM trapsPeter Maydell1-7/+36
2016-02-26target-arm: Fix handling of SDCR for 32-bit codePeter Maydell1-8/+15
2016-02-26target-arm: Make Monitor->NS PL1 mode changes illegal if HCR.TGE is 1Peter Maydell1-0/+10
2016-02-26target-arm: Make mode switches from Hyp via CPS and MRS illegalPeter Maydell1-2/+10
2016-02-26target-arm: In v8, make illegal AArch32 mode changes set PSTATE.ILPeter Maydell1-3/+12
2016-02-26target-arm: Forbid mode switch to Mon from Secure EL1Peter Maydell1-1/+1
2016-02-26target-arm: Add Hyp mode checks to bad_mode_switch()Peter Maydell1-0/+3
2016-02-26target-arm: Add comment about not implementing NSACR.RFRPeter Maydell1-0/+3
2016-02-26target-arm: In cpsr_write() ignore mode switches from User modePeter Maydell1-0/+1
2016-02-26target-arm: Raw CPSR writes should skip checks and bank switchingPeter Maydell1-2/+3
2016-02-26target-arm: Add write_type argument to cpsr_write()Peter Maydell1-1/+2
2016-02-18target-arm: Add PMUSERENR_EL0 registerAlistair Francis1-0/+6
2016-02-18target-arm: Add the pmovsclr_el0 and pmintenclr_el1 registersAlistair Francis1-0/+12
2016-02-18target-arm: Add the pmceid0 and pmceid1 registersAlistair Francis1-0/+16
2016-02-18target-arm: Move bank_number() into internals.hPeter Maydell1-25/+0
2016-02-18target-arm: Move get/set_r13_banked() to op_helper.cPeter Maydell1-33/+0
2016-02-18target-arm: Report correct syndrome for FPEXC32_EL2 trapsPeter Maydell1-2/+2
2016-02-18target-arm: Implement MDCR_EL3.TDA and MDCR_EL2.TDA trapsPeter Maydell1-9/+30
2016-02-18target-arm: Implement MDCR_EL2.TDRA trapsPeter Maydell1-3/+24
2016-02-18target-arm: Implement MDCR_EL3.TDOSA and MDCR_EL2.TDOSA trapsPeter Maydell1-1/+22
2016-02-18target-arm: correct CNTFRQ access rightsPeter Maydell1-3/+26
2016-02-11target-arm: Implement NSACR trapping behaviourPeter Maydell1-4/+58
2016-02-11target-arm: Add isread parameter to CPAccessFnsPeter Maydell1-29/+52
2016-02-11target-arm: Use access_trap_aa32s_el1() for SCR and MVBARPeter Maydell1-2/+4
2016-02-11target-arm: Implement MDCR_EL3 and SDCRPeter Maydell1-0/+26
2016-02-03target-arm: Implement the S2 MMU inputsize > pamax checkEdgar E. Iglesias1-0/+8
2016-02-03target-arm: Rename check_s2_startlevel to check_s2_mmu_setupEdgar E. Iglesias1-6/+6
2016-02-03target-arm: Apply S2 MMU startlevel table size check to AArch64Edgar E. Iglesias1-8/+8
2016-02-03target-arm: Make various system registers visible to EL3Peter Maydell1-29/+29
2016-01-21target-arm: Implement FPEXC32_EL2 system registerPeter Maydell1-0/+16
2016-01-21target-arm: Fix wrong AArch64 entry offset for EL2/EL3 targetPeter Maydell1-1/+20
2016-01-21target-arm: Pull semihosting handling out to arm_cpu_do_interrupt()Peter Maydell1-39/+81
2016-01-21target-arm: Use a single entry point for AArch64 and AArch32 exceptionsPeter Maydell1-31/+44
2016-01-21target-arm: Move aarch64_cpu_do_interrupt() to helper.cPeter Maydell1-0/+100
2016-01-21target-arm: Support multiple address spaces in page table walksPeter Maydell1-2/+6
2016-01-21target-arm: Implement cpu_get_phys_page_attrs_debugPeter Maydell1-4/+5
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