summaryrefslogtreecommitdiff
path: root/target-arm/cpu.h
AgeCommit message (Expand)AuthorFilesLines
2013-02-16target-arm: Update ARMCPU to QOM realizefnAndreas Färber1-0/+1
2012-12-19fpu: move public header file to include/fpuPaolo Bonzini1-1/+1
2012-12-19exec: move include files to include/exec/Paolo Bonzini1-3/+3
2012-10-31cpus: Pass CPUState to [qemu_]cpu_has_work()Andreas Färber1-1/+3
2012-10-05target-arm: Drop unused DECODE_CPREG_CRN macroPeter Maydell1-2/+0
2012-09-15target-arm: final conversion to AREG0 free modeBlue Swirl1-4/+6
2012-08-10target-arm: Fix typos in commentsPeter Maydell1-1/+1
2012-07-12target-arm: Add 64 bit PAR, TTBR0, TTBR1 for LPAEPeter Maydell1-2/+5
2012-07-12target-arm: Extend feature flags to 64 bitsPeter Maydell1-3/+3
2012-07-12target-arm: Implement privileged-execute-never (PXN)Peter Maydell1-0/+2
2012-07-12ARM: Make target_phys_addr_t 64 bits and physaddrs 40 bitsPeter Maydell1-1/+1
2012-06-20target-arm: Remove ARM_CPUID_* macrosPeter Maydell1-27/+0
2012-06-20target-arm: Remove c0_cachetype CPUARMState fieldPeter Maydell1-2/+1
2012-06-20target-arm: Convert MPIDRPeter Maydell1-0/+1
2012-06-20target-arm: Convert cp15 cache ID registersPeter Maydell1-2/+0
2012-06-20target-arm: Convert cp15 crn=0 crm={1,2} feature registersPeter Maydell1-2/+0
2012-06-20target-arm: convert cp15 crn=7 registersPeter Maydell1-0/+3
2012-06-20target-arm: Convert cp15 crn=15 registersPeter Maydell1-0/+1
2012-06-20target-arm: Remove old cpu_arm_set_cp_io infrastructurePeter Maydell1-10/+0
2012-06-20target-arm: initial coprocessor register frameworkPeter Maydell1-0/+201
2012-05-10target-arm/cpu.h: Make cpu_init("nonexistent cpu") return NULLPeter Maydell1-1/+9
2012-04-27target-arm: Change cpu_arm_init() return type to ARMCPUAndreas Färber1-3/+4
2012-04-21target-arm: Move feature bit settings to CPU init fnsPeter Maydell1-3/+3
2012-04-21target-arm: remind to keep arm features in sync with linux-user/elfload.cBenoit Canet1-0/+4
2012-04-06Userspace ARM BE8 supportPaul Brook1-2/+30
2012-03-30ARM: Permit any ARMv6K CPU to read the MVFR0 and MVFR1 VFP registers.Andrew Towers1-0/+1
2012-03-29target-arm: Minimalistic CPU QOM'ificationAndreas Färber1-0/+1
2012-03-29target-arm: Drop cpu_arm_close()Andreas Färber1-1/+0
2012-03-14Rename CPUState -> CPUArchStateAndreas Färber1-1/+1
2012-03-14target-arm: Don't overuse CPUStateAndreas Färber1-5/+5
2012-01-25Add Cortex-A15 CPU definitionPeter Maydell1-0/+1
2012-01-25Add dummy implementation of generic timer cp15 registersPeter Maydell1-0/+1
2012-01-13arm: Add dummy support for co-processor 15's secure config registerRob Herring1-1/+2
2012-01-05arm: add dummy A9-specific cp15 registersMark Langsdorf1-1/+5
2011-10-19target-arm: Implement VFPv4 fused multiply-accumulate insnsPeter Maydell1-0/+1
2011-10-19target-arm: Add ARM UDIV/SDIV supportPeter Maydell1-0/+1
2011-10-19target-arm: Rename ARM_FEATURE_DIV to _THUMB_DIVPeter Maydell1-1/+1
2011-08-09Merge remote-tracking branch 'pm-arm/for-upstream' into pmEdgar E. Iglesias1-0/+2
2011-08-07Remove unused is_softmmu parameter from cpu_handle_mmu_faultBlue Swirl1-1/+1
2011-07-26target-arm: Mark 1136r1 as a v6K corePeter Maydell1-0/+1
2011-07-26target-arm: support for ARM1176JZF-s coresJamie Iles1-0/+1
2011-07-20Merge branch 'for-upstream' of git://git.linaro.org/people/pmaydell/qemu-armBlue Swirl1-1/+7
2011-07-04arm: Add const attribute to some arm_boot_info pointersStefan Weil1-1/+1
2011-06-26Move cpu_has_work and cpu_pc_from_tb to cpu.hBlue Swirl1-0/+13
2011-06-22target-arm: Minimal implementation of performance countersPeter Maydell1-1/+7
2011-05-08target-arm: Privatize CPU_INTERRUPT_FIQ.Richard Henderson1-0/+4
2011-04-20Implement basic part of SA-1110/SA-1100Dmitry Eremin-Solenikov1-0/+3
2011-04-10arm: basic support for ARMv4/ARMv4T emulationDmitry Eremin-Solenikov1-1/+3
2011-03-06target-arm: Implement cp15 VA->PA translationAdam Lackorzynski1-1/+2
2011-02-11arm: drop unused irq-related part of CPUARMStateDmitry Eremin-Solenikov1-4/+0
generated by cgit v1.2.3 (git 2.25.1) at 2024-12-01 20:44:59 +0000