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2015-05-18target-alpha: Raise IOV from CVTQLRichard Henderson1-29/+5
Even if an exception isn't taken, the status flags need updating and the result should be written to the destination. Move the body of cvtql out of line, since we now always need a call. Reported-by: Al Viro <viro@ZenIV.linux.org.uk> Signed-off-by: Richard Henderson <rth@twiddle.net>
2015-05-18target-alpha: Raise EXC_M_INV properly for fp inputsRichard Henderson1-0/+7
Ignore DNZ if software completion isn't used. Raise INV for denormals in system mode so the OS completion handler sees them. Reported-by: Al Viro <viro@ZenIV.linux.org.uk> Signed-off-by: Richard Henderson <rth@twiddle.net>
2015-05-18target-alpha: Disallow literal operand to 1C.30 to 1C.37Richard Henderson1-2/+17
Before 64f45e49 we used to have literal checks for 4 of these 8 opcodes. Confirmed that real hardware doesn't allow them. Reported-by: Al Viro <viro@ZenIV.linux.org.uk> Signed-off-by: Richard Henderson <rth@twiddle.net>
2015-05-18target-alpha: Implement WH64ENRichard Henderson1-0/+4
Backward compatible cache insn introduced for EV7. Reported-by: Al Viro <viro@ZenIV.linux.org.uk> Signed-off-by: Richard Henderson <rth@twiddle.net>
2015-05-18target-alpha: Fix integer overflow checking insnsRichard Henderson1-7/+53
We need to write the result to the destination register before raising any exception. Thus inline the code for each insn, and check for any exception after we're done. Reported-by: Al Viro <viro@ZenIV.linux.org.uk> Signed-off-by: Richard Henderson <rth@twiddle.net>
2015-05-18target-alpha: Raise IOV from CVTTQRichard Henderson1-13/+4
Floating-point overflow is a different bit from integer overflow. Reported-by: Al Viro <viro@ZenIV.linux.org.uk> Signed-off-by: Richard Henderson <rth@twiddle.net>
2015-05-18target-alpha: Set fpcr_exc_status even for disabled exceptionsRichard Henderson1-15/+13
The qualifiers can suppress the raising of exceptions, but real hardware still records that the exceptions occurred. Reported-by: Al Viro <viro@ZenIV.linux.org.uk> Signed-off-by: Richard Henderson <rth@twiddle.net>
2015-05-18target-alpha: Tidy FPCR representationRichard Henderson1-37/+8
Store the fpcr as the hardware represents it. Convert the softfpu representation of exceptions into the fpcr representation. Signed-off-by: Richard Henderson <rth@twiddle.net>
2015-05-18target-alpha: Forget installed round mode after MT_FPCRRichard Henderson1-0/+5
When we use QUAL_RM_D, we copy fpcr_dyn_round to float_status. When we install a new FPCR value, we update fpcr_dyn_round. Reset the status of the cache so that we re-copy for the next fp insn that requires dynamic rounding. Signed-off-by: Richard Henderson <rth@twiddle.net>
2015-05-18target-alpha: Rename floating-point subroutinesRichard Henderson1-34/+34
... to match the instructions, which have no leading "f". Signed-off-by: Richard Henderson <rth@twiddle.net>
2015-03-13tcg: Change translator-side labels to a pointerRichard Henderson1-2/+2
This is improved type checking for the translators -- it's no longer possible to accidentally swap arguments to the branch functions. Note that the code generating backends still manipulate labels as int. With notable exceptions, the scope of the change is just a few lines for each target, so it's not worth building extra machinery to do this change in per-target increments. Cc: Peter Maydell <peter.maydell@linaro.org> Cc: Edgar E. Iglesias <edgar.iglesias@gmail.com> Cc: Michael Walle <michael@walle.cc> Cc: Leon Alrae <leon.alrae@imgtec.com> Cc: Anthony Green <green@moxielogic.com> Cc: Jia Liu <proljc@gmail.com> Cc: Alexander Graf <agraf@suse.de> Cc: Aurelien Jarno <aurelien@aurel32.net> Cc: Blue Swirl <blauwirbel@gmail.com> Cc: Guan Xuetao <gxt@mprc.pku.edu.cn> Cc: Paolo Bonzini <pbonzini@redhat.com> Cc: Max Filippov <jcmvbkbc@gmail.com> Reviewed-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de> Signed-off-by: Richard Henderson <rth@twiddle.net>
2015-02-12tcg: Introduce tcg_op_buf_count and tcg_op_buf_fullRichard Henderson1-7/+7
The method by which we count the number of ops emitted is going to change. Abstract that away into some inlines. Reviewed-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de> Signed-off-by: Richard Henderson <rth@twiddle.net>
2015-02-12tcg: Move emit of INDEX_op_end into gen_tb_endRichard Henderson1-1/+1
Reviewed-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de> Signed-off-by: Richard Henderson <rth@twiddle.net>
2015-01-03gen-icount: check cflags instead of use_icount globalPaolo Bonzini1-1/+1
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com> Signed-off-by: Pavel Dovgalyuk <pavel.dovgaluk@ispras.ru> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2015-01-03translate: check cflags instead of use_icount globalPaolo Bonzini1-4/+4
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com> Signed-off-by: Pavel Dovgalyuk <pavel.dovgaluk@ispras.ru> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2014-08-12trace: [tcg] Include TCG-tracing header on all targetsLluís Vilanova1-0/+3
Signed-off-by: Lluís Vilanova <vilanova@ac.upc.edu> Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
2014-06-05softmmu: introduce cpu_ldst.hPaolo Bonzini1-0/+1
This will collect all load and store helpers soon. For now it is just a replacement for softmmu_exec.h, which this patch stops including directly, but we also include it where this will be necessary in order to simplify the next patch. Reviewed-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2014-05-28tcg: Invert the inclusion of helper.hRichard Henderson1-3/+2
Rather than include helper.h with N values of GEN_HELPER, include a secondary file that sets up the macros to include helper.h. This minimizes the files that must be rebuilt when changing the macros for file N. Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Signed-off-by: Richard Henderson <rth@twiddle.net>
2014-05-02target-alpha: Fix RDUSPRichard Henderson1-1/+1
Commit 06ef8604e92964cbf30084b7d31091aa7cbbb62f contained a typo. Signed-off-by: Richard Henderson <rth@twiddle.net>
2014-04-17target-alpha: Remove cpu_unique, cpu_sysval, cpu_uspRichard Henderson1-19/+18
Technically, these variables could have been referenced both via offsets from env and as TCG registers, which would be illegal. Of course, that could only be done from PALcode, and ours doesn't do that. But honestly, these are used infrequently enough that they don't really need to be TCG registers. We wind up with exactly the same code if we follow the letter of the law and issue explicit ld/st. Signed-off-by: Richard Henderson <rth@twiddle.net>
2014-04-17target-alpha: Tidy alpha_translate_initRichard Henderson1-35/+43
Signed-off-by: Richard Henderson <rth@twiddle.net>
2014-04-17target-alpha: Don't issue goto_tb under singlestepRichard Henderson1-1/+2
Signed-off-by: Richard Henderson <rth@twiddle.net>
2014-04-17target-alpha: Use non-local temps for zero/sinkRichard Henderson1-2/+2
These values are no longer live across branches. Signed-off-by: Richard Henderson <rth@twiddle.net>
2014-04-17target-alpha: Use extract to get insn fieldsRichard Henderson1-27/+22
Signed-off-by: Richard Henderson <rth@twiddle.net>
2014-04-17target-alpha: Convert mfpr/mtpr to source/sinkRichard Henderson1-33/+19
Signed-off-by: Richard Henderson <rth@twiddle.net>
2014-04-17target-alpha: Convert gen_cpys et al to source/sinkRichard Henderson1-76/+24
Signed-off-by: Richard Henderson <rth@twiddle.net>
2014-04-17target-alpha: Convert gen_fcvtlq/ql to source/sinkRichard Henderson1-50/+28
Signed-off-by: Richard Henderson <rth@twiddle.net>
2014-04-17target-alpha: Convert gen_fcmov to source/sinkRichard Henderson1-30/+14
Signed-off-by: Richard Henderson <rth@twiddle.net>
2014-04-17target-alpha: Convert gen_bcond to source/sinkRichard Henderson1-18/+6
Signed-off-by: Richard Henderson <rth@twiddle.net>
2014-04-17target-alpha: Convert most ieee insns to source/sinkRichard Henderson1-52/+17
This one fixes a bug, previously noted as supressing exceptions in the (unlikely) case the destination register was $f31. Signed-off-by: Richard Henderson <rth@twiddle.net>
2014-04-17target-alpha: Convert gen_ieee_input to source/sinkRichard Henderson1-19/+13
Signed-off-by: Richard Henderson <rth@twiddle.net>
2014-04-17target-alpha: Convert MVIOP2 to source/sinkRichard Henderson1-19/+4
Signed-off-by: Richard Henderson <rth@twiddle.net>
2014-04-17target-alpha: Convert ARITH3 to source/sinkRichard Henderson1-69/+39
Signed-off-by: Richard Henderson <rth@twiddle.net>
2014-04-17target-alpha: Convert FARITH3 to source/sinkRichard Henderson1-53/+12
Signed-off-by: Richard Henderson <rth@twiddle.net>
2014-04-17target-alpha: Convert FARITH2 to source/sinkRichard Henderson1-32/+11
Signed-off-by: Richard Henderson <rth@twiddle.net>
2014-04-17target-alpha: Convert gen_zap/not to source/sinkRichard Henderson1-30/+11
Signed-off-by: Richard Henderson <rth@twiddle.net>
2014-04-17target-alpha: Convert gen_ins_h/l to source/sinkRichard Henderson1-61/+50
Signed-off-by: Richard Henderson <rth@twiddle.net>
2014-04-17target-alpha: Convert gen_ext_h/l to source/sinkRichard Henderson1-40/+26
Signed-off-by: Richard Henderson <rth@twiddle.net>
2014-04-17target-alpha: Convert gen_msk_h/l to source/sinkRichard Henderson1-28/+19
Signed-off-by: Richard Henderson <rth@twiddle.net>
2014-04-17target-alpha: Convert gen_cmov to source/sinkRichard Henderson1-44/+22
Signed-off-by: Richard Henderson <rth@twiddle.net>
2014-04-17target-alpha: Convert ARITH3_EX to source/sinkRichard Henderson1-43/+6
Signed-off-by: Richard Henderson <rth@twiddle.net>
2014-04-17target-alpha: Convert gen_cmp to source/sinkRichard Henderson1-35/+5
Signed-off-by: Richard Henderson <rth@twiddle.net>
2014-04-17target-alpha: Convert gen_store_conditional to source/sinkRichard Henderson1-5/+1
Signed-off-by: Richard Henderson <rth@twiddle.net>
2014-04-17target-alpha: Convert gen_load/store_mem to source/sinkRichard Henderson1-38/+29
Signed-off-by: Richard Henderson <rth@twiddle.net>
2014-04-17target-alpha: Convert opcode 0x1F to source/sinkRichard Henderson1-20/+10
Signed-off-by: Richard Henderson <rth@twiddle.net>
2014-04-17target-alpha: Convert opcode 0x1E to source/sinkRichard Henderson1-2/+4
Signed-off-by: Richard Henderson <rth@twiddle.net>
2014-04-17target-alpha: Convert opcode 0x1C to source/sinkRichard Henderson1-54/+19
Signed-off-by: Richard Henderson <rth@twiddle.net>
2014-04-17target-alpha: Convert opcode 0x1B to source/sinkRichard Henderson1-19/+13
Signed-off-by: Richard Henderson <rth@twiddle.net>
2014-04-17target-alpha: Convert opcode 0x1A to source/sinkRichard Henderson1-5/+4
Signed-off-by: Richard Henderson <rth@twiddle.net>
2014-04-17target-alpha: Convert opcode 0x18 to source/sinkRichard Henderson1-9/+9
Signed-off-by: Richard Henderson <rth@twiddle.net>
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