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path: root/hw/sh7750.c
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2009-06-16Remove io_index argument from cpu_register_io_memory()Avi Kivity1-4/+2
The parameter is always zero except when registering the three internal io regions (ROM, unassigned, notdirty). Remove the parameter to reduce the API's power, thus facilitating future change. Signed-off-by: Avi Kivity <avi@redhat.com> Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
2009-05-13Include assert.h from qemu-common.hPaul Brook1-1/+0
Include assert.h from qemu-common.h and remove other direct uses. cpu-all.h still need to include it because of the dyngen-exec.h hacks Signed-off-by: Paul Brook <paul@codesourcery.com>
2009-02-07SH7750/51: add register BCR3, BCR4, PCR, RTCOR, RTCNT, RTCSR, SDMR2, SDMR3 ↵aurel321-10/+42
and fix BCR2 support Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net> git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6548 c046a42c-6fe2-441c-8c8c-71466251a162
2008-12-13Remove unnecessary trailing newlinesblueswir11-1/+0
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6000 c046a42c-6fe2-441c-8c8c-71466251a162
2008-12-07SH4: Eliminate P4 to A7 mangling (Takashi YOSHII).balrog1-0/+6
Main purpose of this is to delete *physical = address & 0x1fffffff; at target-sh4/helper.c:449, using new mmio rule introduced by #5849 This masking is a nice trick to realize P4/A7 duality of SH registers. But, IMHO, it is logically wrong. Most of SH4 cpu control registers in P4 area(0xfc000000...0xffffffff) have one more address called A7 which is usually P4 address with upper 3bits masked. This is an address only appears in TLB's physical address part. Current code use trick writing drivers as if they are really in A7 (that's why you see many *_A7 in hw/sh*.c), and using translation P4 to A7. Signed-off-by: Takashi YOSHII <takasi-y@ops.dti.ne.jp> Signed-off-by: Andrzej Zaborowski <andrew.zaborowski@intel.com> git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5935 c046a42c-6fe2-441c-8c8c-71466251a162
2008-12-07SH: improve the way sh7750 registers io memory (Takashi YOSHII).balrog1-8/+6
Fixes to be needed for commit #5849 "Change MMIO callbacks..." hw/sh7750.c: - Divide region of CPU control registers to avoid overlapping to peripheral modules. - Delete unused var "icr", which had moved to hw/sh_intc.c. hw/sm501.c: - Merge non page aligned palette registers into the region of control registers. Signed-off-by: Takashi YOSHII <takasi-y@ops.dti.ne.jp> Signed-off-by: Andrzej Zaborowski <andrew.zaborowski@intel.com> git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5934 c046a42c-6fe2-441c-8c8c-71466251a162
2008-12-07SH: r2d pci support (Takashi YOSHII).balrog1-0/+17
This patch adds pci support to sh/r2d board. This is the first user of PCIC support I formerly sent. PCIC actually is inside of chip with CPU core on SH7751. But, this code is written as if SH7750 and PCIC are on board. I care little about physical device boundary, but fitting with qemu's design. This patch also adds some BSC (Bus State Controller) registers, because PCI device driver software have to accesses them. Signed-off-by: Takashi YOSHII <takasi-y@ops.dti.ne.jp> Signed-off-by: Andrzej Zaborowski <andrew.zaborowski@intel.com> git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5932 c046a42c-6fe2-441c-8c8c-71466251a162
2008-12-07sh4: Add IRL (4-bit encoded interrupt input) support (Takashi YOSHII).balrog1-1/+39
This patch adds IRL(4bit encoded 15 level interrupt input) support to SH using qemu_irq as a multi level (!=on/off) signal. Signed-off-by: Takashi YOSHII <takasi-y@ops.dti.ne.jp> Signed-off-by: Andrzej Zaborowski <andrew.zaborowski@intel.com> git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5925 c046a42c-6fe2-441c-8c8c-71466251a162
2008-12-01Change MMIO callbacks to use offsets, not absolute addresses.pbrook1-1/+2
Signed-off-by: Paul Brook <paul@codesourcery.com> git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5849 c046a42c-6fe2-441c-8c8c-71466251a162
2008-11-21SH4: Switch serial emulation to qemu_irqaurel321-8/+8
This patches makes SH serial emulation use qemu_irq in its interface. * hw/sh.h (sh_serial_init): Take qemu_irq, not intc_source. * hw/sh7750.c (sh7750_init): Adjust. * hw/sh_intc.c (sh_intc_set_irq): Don't assert or deassert irq more than once. * hw/sh_serial.c (sh_serial_state): Use qemu_irq, not intc_source. (sh_serial_clear_fifo, sh_serial_ioport_write) (sh_serial_receive_byte): Adjust. (sh_serial_init): Take qemu_irq, not intc_source. (Vladimir Prus) git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5769 c046a42c-6fe2-441c-8c8c-71466251a162
2008-11-21SH4: Use qemu_irq in timer emulation.aurel321-6/+6
* hw/sh.h (tmu012_init): Accept qemu_irq, not intc_source. * hw/sh7750.c (sh7750_init): Pass qemu_irq to tmu012_init. * hw/sh_intc.c (sh_intc_set_irq): New. (sh_intc_init): Allocate irqs. * hw/sh_intc.h (struct intc_desc): New field irqs. * hw/sh_timer.c (sh_timer_state): Use qemu_irq, not intc_source. (sh_timer_update): Use qemu_set_irq, not sh_intc_toggle_source. (sh_timer_init, tmu012_init): Adjust. (Vladimir Prus) git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5768 c046a42c-6fe2-441c-8c8c-71466251a162
2008-09-02sh4: CPU versioning.aurel321-26/+17
Trivial patch adding CPU listing and the ability to do per-subtype CVR/PVR/PRR values. Presently SH7750R and SH7751R definitions are provided, as these are the ones in present use in-tree. The CVR value for SH7751R is intentionally restricted so the kernel boots, though this will want to be switched to the proper CVR value once system emulation has sufficiently stabilized. This also makes it trivial to abstract subtype specific registers like MMU_PTEA and to set up feature bits in line with the kernel probing for things like conditionalizing FPU/DSP context. Signed-off-by: Paul Mundt <lethal@linux-sh.org> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net> git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5133 c046a42c-6fe2-441c-8c8c-71466251a162
2008-08-22[sh4] MMU bug fixaurel321-0/+4
Some bugs on SH4 MMU are fixed. - When a TLB entry is overwritten or invalidated, tlb_flush_page() should be invoked to invalidate old entry. - When a ASID is changed, tlb_flush() should be invoke to invalidate entries which have old ASID. - The check for shared bit in TLB entry causes multiple TLB hit exception. As SH3's MMU, shared bit is ignored. - ASID is used when MMUCR's SV bit or SR's MD bit is zero. No need to check both bits are zero. (Shin-ichiro KAWASAKI) git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5068 c046a42c-6fe2-441c-8c8c-71466251a162
2008-08-22[sh4] memory mapped TLB entriesaurel321-0/+110
SH4 MMU's memory mapped TLB feature is implemented. SH-Linux seems to write to memory mapped TLB to invalidate a TLB entry, but does not to read it. So only memory write feature is implemented. Work on memory read feature is left. (Shin-ichiro KAWASAKI) git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5067 c046a42c-6fe2-441c-8c8c-71466251a162
2008-07-16Fix a bunch of type mismatch-related warnings (Jan Kiszka).balrog1-2/+2
Fix a typo in my previous comming (spotted by Laurent Desnouges). git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4877 c046a42c-6fe2-441c-8c8c-71466251a162
2008-05-09SH4 serial controler improvementsaurel321-2/+12
(Shin-ichiro KAWASAKI) git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4397 c046a42c-6fe2-441c-8c8c-71466251a162
2008-05-09SH4 MMU improvementsaurel321-0/+3
(Shin-ichiro KAWASAKI) git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4396 c046a42c-6fe2-441c-8c8c-71466251a162
2007-12-12Adds interrupt support to the sh specific timer code (Magnus Damm).balrog1-3/+9
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3812 c046a42c-6fe2-441c-8c8c-71466251a162
2007-12-02SH4: system emulator interrupt update, by Magnus Damm.ths1-0/+2
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3762 c046a42c-6fe2-441c-8c8c-71466251a162
2007-11-17Break up vl.h.pbrook1-1/+3
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3674 c046a42c-6fe2-441c-8c8c-71466251a162
2007-11-11removed invalid use of _INTC_ARRAYbellard1-2/+2
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3602 c046a42c-6fe2-441c-8c8c-71466251a162
2007-10-04sh775x interrupt controller by Magnus Damm.balrog1-45/+178
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3327 c046a42c-6fe2-441c-8c8c-71466251a162
2007-09-29Add FRQCR read support, by Magnus Damm.ths1-0/+2
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3272 c046a42c-6fe2-441c-8c8c-71466251a162
2007-09-29Add INTC controller prototype, by Magnus Damm.ths1-0/+51
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3271 c046a42c-6fe2-441c-8c8c-71466251a162
2007-09-29Stand-alone SCI/SCIF emulation code, by Magnus Damm.ths1-341/+4
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3270 c046a42c-6fe2-441c-8c8c-71466251a162
2007-09-29Stand-alone TMU emulation code, by Magnus Damm.ths1-96/+6
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3269 c046a42c-6fe2-441c-8c8c-71466251a162
2007-09-16find -type f | xargs sed -i 's/[\t ]$//g' # on most filesths1-2/+2
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3173 c046a42c-6fe2-441c-8c8c-71466251a162
2007-01-27Rearrange char event handlers to fix CHR_EVENT_RESET.pbrook1-6/+4
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@2361 c046a42c-6fe2-441c-8c8c-71466251a162
2006-06-25C99 64 bit printfbellard1-1/+1
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@2018 c046a42c-6fe2-441c-8c8c-71466251a162
2006-04-27SHIX board emulation (Samuel Tardieu)bellard1-0/+836
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@1862 c046a42c-6fe2-441c-8c8c-71466251a162
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