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2014-07-09mips_malta: Remove incorrect KVM T&E referencesJames Hogan1-3/+3
Fix the error message and code comments relating to KVM not supporting booting from the flash mapping when no kernel is provided. The issue is a general MIPS KVM issue and isn't specific to the Trap & Emulate version of MIPS KVM. Cc: Aurelien Jarno <aurelien@aurel32.net> Cc: Paolo Bonzini <pbonzini@redhat.com> Reported-by: Andreas Färber <afaerber@suse.de> Signed-off-by: James Hogan <james.hogan@imgtec.com> Reviewed-by: Aurelien Jarno <aurelien@aurel32.net> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2014-06-20gt64xxx_pci: Add VMStateDescriptionSanjay Lal1-0/+23
Add VMStateDescription for GT64120 PCI emulation used by the Malta platform, to allow it to work with savevm/loadvm and live migration. The entire register array is saved/restored using VMSTATE_UINT32_ARRAY (fixed length GT_REGS = 1024). Signed-off-by: Sanjay Lal <sanjayl@kymasys.com> [james.hogan@imgtec.com: Convert to VMState] Signed-off-by: James Hogan <james.hogan@imgtec.com> Cc: Andreas Färber <afaerber@suse.de> Reviewed-by: Aurelien Jarno <aurelien@aurel32.net> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2014-06-20Merge remote-tracking branch 'remotes/kvm/uq/master' into stagingPeter Maydell4-25/+90
* remotes/kvm/uq/master: hw/mips: malta: Don't boot from flash with KVM T&E MAINTAINERS: Add entry for MIPS KVM target-mips: Enable KVM support in build system hw/mips: malta: Add KVM support hw/mips: In KVM mode, inject IRQ2 (I/O) interrupts via ioctls target-mips: Call kvm_mips_reset_vcpu() from mips_cpu_reset() target-mips: kvm: Add main KVM support for MIPS kvm: Allow arch to set sigmask length target-mips: get_physical_address: Add KVM awareness target-mips: get_physical_address: Add defines for segment bases hw/mips: Add API to convert KVM guest KSEG0 <-> GPA hw/mips/cputimer: Don't start periodic timer in KVM mode target-mips: Reset CPU timer consistently KVM: Fix GSI number space limit Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2014-06-20hw/mips: malta: Don't boot from flash with KVM T&EJames Hogan1-0/+6
In KVM trap & emulate (T&E) mode the flash reset region at 0xbfc00000 isn't executable, which is why the minimal kernel bootloader is loaded and executed from the last 1MB of DRAM instead. Therefore if no kernel is provided on the command line and KVM is enabled, exit with an error since booting from flash will fail. Reported-by: Aurelien Jarno <aurelien@aurel32.net> Signed-off-by: James Hogan <james.hogan@imgtec.com> Cc: Paolo Bonzini <pbonzini@redhat.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2014-06-19pc: add acpi-device link to PCMachineStateIgor Mammedov1-1/+1
the link will used later to access device implementing ACPI functions instead of adhoc lookup in QOM tree. Signed-off-by: Igor Mammedov <imammedo@redhat.com> Acked-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
2014-06-18hw/mips: malta: Add KVM supportJames Hogan1-20/+53
In KVM mode the bootrom is loaded and executed from the last 1MB of DRAM. Based on "[PATCH 12/12] KVM/MIPS: General KVM support and support for SMP Guests" by Sanjay Lal <sanjayl@kymasys.com>. Signed-off-by: James Hogan <james.hogan@imgtec.com> Reviewed-by: Aurelien Jarno <aurelien@aurel32.net> Cc: Peter Maydell <peter.maydell@linaro.org> Cc: Sanjay Lal <sanjayl@kymasys.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2014-06-18hw/mips: In KVM mode, inject IRQ2 (I/O) interrupts via ioctlsSanjay Lal1-0/+11
COP0 emulation is in-kernel for KVM, so inject IRQ2 (I/O) interrupts via ioctls. Signed-off-by: Sanjay Lal <sanjayl@kymasys.com> Signed-off-by: James Hogan <james.hogan@imgtec.com> Reviewed-by: Aurelien Jarno <aurelien@aurel32.net> Reviewed-by: Andreas Färber <afaerber@suse.de> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2014-06-18hw/mips: Add API to convert KVM guest KSEG0 <-> GPASanjay Lal1-1/+6
Add API for converting physical addresses to KVM guest KSEG0 addresses, and fix the existing API for converting KSEG0 addresses to physical addresses to work in the KVM case. Both have the same sized KSEG0, so it's just a case of fixing the mask. In KVM trap and emulate mode both the guest kernel and guest userspace execute in useg: Guest User address space: 0x00000000..0x3fffffff Guest Kernel Unmapped: 0x40000000..0x5fffffff Guest Kernel Mapped: 0x60000000..0x7fffffff Signed-off-by: Sanjay Lal <sanjayl@kymasys.com> Signed-off-by: James Hogan <james.hogan@imgtec.com> Cc: Aurelien Jarno <aurelien@aurel32.net> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2014-06-18hw/mips/cputimer: Don't start periodic timer in KVM modeSanjay Lal1-1/+8
Compare/Count timer interrupts are handled in-kernel for KVM. Therefore don't bother creating the timer at init time if KVM is enabled. This will conveniently avoid attempts to set the timeout when cpu_mips_store_count() is called at reset with KVM enabled, treating the timer as stopped so that CP0_Count is modified directly. Signed-off-by: Sanjay Lal <sanjayl@kymasys.com> [james.hogan@imgtec.com: Update after "target-mips: Reset CPU timer consistently" which moves timer start to reset time] Signed-off-by: James Hogan <james.hogan@imgtec.com> Cc: Aurelien Jarno <aurelien@aurel32.net> Cc: Paolo Bonzini <pbonzini@redhat.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2014-06-18target-mips: Reset CPU timer consistentlyJames Hogan1-3/+6
The MIPS CPU timer (CP0 Count/Compare registers & QEMU timer) is reset at machine initialisation, including starting the timeout. Both registers however are placed before mvp in CPUMIPSState so they will both be zeroed on reset by the memset in mips_cpu_reset() including soon after init. This doesn't take into account that the timer may be running, in which case env->CP0_Count will represent the delta against the VM clock and the timeout will need updating. At init time (cpu_mips_clock_init()), lets only create the timer. Setting Count = 1 and starting the timer (cpu_mips_store_count()) can be done at reset time from cpu_state_reset(), which is after the memset. There is also no need to set CP0_Compare = 0 as that is already handled by the memset. Note that a reset occurs from mips_cpu_realizefn() which is before the machine init callback has had a chance to set up the CPU interrupts and the CPU timer, so env->timer will be NULL. This case is handled explicitly in cpu_mips_store_count(), treating the timer as disabled (which will also be the right thing to do when KVM support is added). Reported-by: Paolo Bonzini <pbonzini@redhat.com> Signed-off-by: James Hogan <james.hogan@imgtec.com> Cc: Aurelien Jarno <aurelien@aurel32.net> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2014-06-05hw: use ld_p/st_p instead of ld_raw/st_rawPaolo Bonzini2-102/+102
The ld_raw and st_raw definitions are only needed in code that must compile for both user-mode and softmmu emulation. Device models can use the equivalent ld_p/st_p which are simple pointer accessors. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2014-05-28machine: Conversion of QEMUMachineInitArgs to MachineStateMarcel Apfelbaum5-30/+30
Total removal of QEMUMachineInitArgs struct. QEMUMachineInitArgs's fields are copied into MachineState. Removed duplicated fields from MachineState. All the other changes are only mechanical refactoring, no semantic changes. Signed-off-by: Marcel Apfelbaum <marcel.a@redhat.com> Acked-by: Cornelia Huck <cornelia.huck@de.ibm.com> (s390) Reviewed-by: Michael S. Tsirkin <mst@redhat.com> (PC) [AF: Renamed ms -> machine, use MACHINE_GET_CLASS()] Signed-off-by: Andreas Färber <afaerber@suse.de>
2014-05-07hw/mips: Add missing 'static' and 'const' attributesStefan Weil1-1/+1
This fixes a warning from the static code analysis (smatch). Signed-off-by: Stefan Weil <sw@weilnetz.de> Signed-off-by: Michael Tokarev <mjt@tls.msk.ru> Acked-by: Aurelien Jarno <aurelien@aurel32.net>
2014-02-14i2c: Rename i2c_bus to I2CBusAndreas Färber2-2/+2
Reviewed-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com> Signed-off-by: Andreas Färber <afaerber@suse.de>
2013-12-23pci-host: Consistently set cannot_instantiate_with_device_add_yetMarkus Armbruster1-0/+6
Many PCI host bridges consist of a sysbus device and a PCI device. You need both for the thing to work. Arguably, these bridges should be modelled as a single, composite devices instead of pairs of seemingly independent devices you can only use together, but we're not there, yet. Since the sysbus part can't be instantiated with device_add, yet, permitting it with the PCI part is useless. We shouldn't offer useless options to the user, so let's set cannot_instantiate_with_device_add_yet for them. It's already set for Bonito, Grackle, i440FX and Raven. Document why. Set it for the others: dec-21154, e500-host-bridge, gt64120_pci, mch, pbm-pci, ppc4xx-host-bridge, sh_pci_host, u3-agp, uni-north-agp, uni-north-internal-pci, uni-north-pci, and versatile_pci_host. Signed-off-by: Markus Armbruster <armbru@redhat.com> Reviewed-by: Marcel Apfelbaum <marcel.a@redhat.com> Signed-off-by: Andreas Färber <afaerber@suse.de>
2013-11-21mips jazz: do not raise data bus exception when accessing invalid addressesHervé Poussineau1-0/+24
MIPS Jazz chipset doesn't seem to raise data bus exceptions on invalid accesses. However, there is no easy way to prevent them. Creating a big memory region for the whole address space doesn't prevent memory core to directly call unassigned_mem_read/write which in turn call cpu->do_unassigned_access, which (for MIPS CPU) raise an data bus exception. This fixes a MIPS Jazz regression introduced in c658b94f6e8c206c59d02aa6fbac285b86b53d2c. Signed-off-by: Hervé Poussineau <hpoussin@reactos.org> Reviewed-by: Paolo Bonzini <pbonzini@redhat.com> Signed-off-by: Hervé Poussineau <hpoussin@reactos.org> Message-id: 1383603977-7003-1-git-send-email-hpoussin@reactos.org Signed-off-by: Anthony Liguori <aliguori@amazon.com>
2013-11-05mips_mipssim: Silence BIOS loading warning for qtestAndreas Färber1-1/+3
Reviewed-by: Aurelien Jarno <aurelien@aurel32.net> Signed-off-by: Andreas Färber <afaerber@suse.de>
2013-09-09mips_malta: support up to 2GiB RAMPaul Burton1-8/+28
A Malta board can support up to 2GiB of RAM. Since the unmapped kseg0/1 regions are only 512MiB large & the latter 256MiB of those are taken up by the IO region, access to RAM beyond 256MiB must be done through a mapped region. In the case of a Linux guest this means we need to use highmem. The mainline Linux kernel does not support highmem for Malta at this time, however this can be tested using the linux-mti-3.8 kernel branch available from: git://git.linux-mips.org/pub/scm/linux-mti.git You should be able to boot a Linux kernel built from the linux-mti-3.8 branch, with CONFIG_HIGHMEM enabled, using 2GiB RAM by passing "-m 2G" to QEMU and appending the following kernel parameters: mem=256m@0x0 mem=256m@0x90000000 mem=1536m@0x20000000 Note that the upper half of the physical address space of a Malta mirrors the lower half (hence the 2GiB limit) except that the IO region (0x10000000-0x1fffffff in the lower half) is not mirrored in the upper half. That is, physical addresses 0x90000000-0x9fffffff access RAM rather than the IO region, resulting in a physical address space resembling the following: 0x00000000 -> 0x0fffffff RAM 0x10000000 -> 0x1fffffff I/O 0x20000000 -> 0x7fffffff RAM 0x80000000 -> 0x8fffffff RAM (mirror of 0x00000000 -> 0x0fffffff) 0x90000000 -> 0x9fffffff RAM 0xa0000000 -> 0xffffffff RAM (mirror of 0x20000000 -> 0x7fffffff) The second mem parameter provided to the kernel above accesses the second 256MiB of RAM through the upper half of the physical address space, making use of the aliasing described above in order to avoid the IO region and use the whole 2GiB RAM. The memory setup may be seen as 'backwards' in this commit since the 'real' memory is mapped in the upper half of the physical address space and the lower half contains the aliases. On real hardware it would be typical to see the upper half of the physical address space as the alias since the bus addresses generated match the lower half of the physical address space. However since the memory accessible in the upper half of the physical address space is uninterrupted by the IO region it is easiest to map the RAM as a whole there, and functionally it makes no difference to the target code. Due to the requirements of accessing the second 256MiB of RAM through a mapping to the upper half of the physical address space it is usual for the bootloader to indicate a maximum of 256MiB memory to a kernel. This allows kernels which do not support such access to boot on systems with more than 256MiB of RAM. It is also the behaviour assumed by Linux. QEMUs small generated bootloader is modified to provide this behaviour. Signed-off-by: Paul Burton <paul.burton@imgtec.com> Signed-off-by: Yongbok Kim <yongbok.kim@imgtec.com> Reviewed-by: Aurelien Jarno <aurelien@aurel32.net> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2013-09-03Merge remote-tracking branch 'mst/tags/for_anthony' into stagingAnthony Liguori5-6/+0
pc,pci,virtio fixes and cleanups This includes pc and pci cleanups and enhancements, and a virtio bugfix for level interrupts. Signed-off-by: Michael S. Tsirkin <mst@redhat.com> # gpg: Signature made Sun 01 Sep 2013 03:15:36 AM CDT using RSA key ID D28D5469 # gpg: Can't check signature: public key not found # By Michael S. Tsirkin (3) and others # Via Michael S. Tsirkin * mst/tags/for_anthony: virtio_pci: fix level interrupts with irqfd pc: reduce duplication, fix PIIX descriptions hw: Clean up bogus default boot order pci: add config space access traces pc: fix regression for 64 bit PCI memory pci: Introduce helper to retrieve a PCI device's DMA address space Message-id: 1378023590-11109-1-git-send-email-mst@redhat.com Signed-off-by: Anthony Liguori <anthony@codemonkey.ws>
2013-08-28hw: Clean up bogus default boot orderMarkus Armbruster5-6/+0
We set default boot order "cad" in every single machine definition except "pseries" and "moxiesim", even though very few boards actually care for boot order, and "cad" makes sense for even fewer. Machines that care: * pc and its variants Accept up to three letters 'a', 'b' (undocumented alias for 'a'), 'c', 'd' and 'n'. Reject all others (fatal with -boot). * nseries (n800, n810) Check whether order starts with 'n'. Silently ignored otherwise. * prep, g3beige, mac99 Extract the first character the machine understands (subset of 'a'..'f'). Silently ignored otherwise. * spapr Accept an arbitrary string (vl.c restricts it to contain only 'a'..'p', no duplicates). * sun4[mdc] Use the first character. Silently ignored otherwise. Strip characters these machines ignore from their default boot order. For all other machines, remove the unused default boot order alltogether. Note that my rename of QEMUMachine member boot_order to default_boot_order and QEMUMachineInitArgs member boot_device to boot_order has a welcome side effect: it makes every use of boot orders visible in this patch, for easy review. Signed-off-by: Markus Armbruster <armbru@redhat.com> Reviewed-by: Laszlo Ersek <lersek@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
2013-08-22aio / timers: Switch entire codebase to the new timer APIAlex Bligh1-6/+6
This is an autogenerated patch using scripts/switch-timer-api. Switch the entire code base to using the new timer API. Note this patch may introduce some line length issues. Signed-off-by: Alex Bligh <alex@alex.org.uk> Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
2013-08-22aio / timers: Rename qemu_timer_* functionsAlex Bligh1-2/+2
Rename four functions in preparation for new API. Rename qemu_timer_expired to timer_expired Rename qemu_timer_expire_time_ns to timer_expire_time_ns Rename qemu_timer_pending to timer_pending Rename qemu_timer_expired_ns to timer_expired_ns Signed-off-by: Alex Bligh <alex@alex.org.uk> Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
2013-08-14mips_malta: do not raise exceptions when accessing invalid memoryAurelien Jarno1-0/+6
Since commit c658b94f6e8c206c59d02aa6fbac285b86b53d2c, MIPS raises exceptions when accessing invalid memory. This is not the correct behaviour for MIPS Malta Core LV, as the GT-64120A system controller just ignore undecoded access. This feature is used by the Linux kernel to probe for some devices. Emulate the correct behaviour in QEMU by adding an empty slot covering the entire memory space decoded by the GT-64120A. Tested-by: Stefan Weil <sw@weilnetz.de> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2013-08-08mips: revert commit b332d24a8e1290954029814d09156b06ede358e2Aurelien Jarno4-9/+14
Now that this code path is not triggered anymore during the tests, revert commit b332d24a8e1290954029814d09156b06ede358e2. Booting a MIPS target without kernel nor bios doesn't really make sense. At the same time replace fprintf(stderr, ...) by error_report(). Reviewed-by: Andreas Färber <afaerber@suse.de> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2013-07-30mips_r4k: Silence BIOS loading warning for qtestAndreas Färber1-2/+2
Signed-off-by: Andreas Färber <afaerber@suse.de> Reviewed-by: Anthony Liguori <aliguori@us.ibm.com> Signed-off-by: Andreas Färber <afaerber@suse.de> Message-id: 1375106733-832-6-git-send-email-afaerber@suse.de Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
2013-07-30mips_jazz: Silence BIOS loading warning for qtestAndreas Färber1-1/+2
Signed-off-by: Andreas Färber <afaerber@suse.de> Reviewed-by: Anthony Liguori <aliguori@us.ibm.com> Signed-off-by: Andreas Färber <afaerber@suse.de> Message-id: 1375106733-832-5-git-send-email-afaerber@suse.de Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
2013-07-30mips_malta: Silence BIOS loading warning for qtestAndreas Färber1-1/+3
Signed-off-by: Andreas Färber <afaerber@suse.de> Reviewed-by: Anthony Liguori <aliguori@us.ibm.com> Signed-off-by: Andreas Färber <afaerber@suse.de> Message-id: 1375106733-832-4-git-send-email-afaerber@suse.de Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
2013-07-30mips_fulong2e: Silence BIOS loading warning for qtestAndreas Färber1-1/+3
Signed-off-by: Andreas Färber <afaerber@suse.de> Reviewed-by: Anthony Liguori <aliguori@us.ibm.com> Signed-off-by: Andreas Färber <afaerber@suse.de> Message-id: 1375106733-832-3-git-send-email-afaerber@suse.de Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
2013-07-29mips_malta: fix copy of the 0x1fc00000 regionAurelien Jarno1-2/+2
Copy the whole 0x1fe000000 region into 0x1fc00000, independently of the loaded BIOS size. This fix the MIPS make check tests. Reported-by: Andreas Färber <afaerber@suse.de> Tested-by: Andreas Färber <afaerber@suse.de> Cc: Paul Burton <paul.burton@imgtec.com> Cc: Leon Alrae <leon.alrae@imgtec.com> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2013-07-29hw/mips: align initrd to 64KB to avoid kernel errorJames Hogan4-4/+4
The Linux kernel can be configured to use 64KB pages, but it also requires initrd to be page aligned. Therefore, to be safe, align the initrd to 64KB using a new INITRD_PAGE_MASK rather than TARGET_PAGE_MASK. Signed-off-by: James Hogan <james.hogan@imgtec.com> Signed-off-by: Leon Alrae <leon.alrae@imgtec.com> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2013-07-28mips_malta: generate SMBUS EEPROM dataPaul Burton1-46/+87
The malta contains 2 EEPROMs, one containing SPD data for the SDRAM and another containing board information such as serial number and MAC address. These are both exposed via the PIIX4 SMBUS. Generating this data and providing it to smbus_eeprom_init will allow YAMON to read a serial number for the board and prevent it from warning that the EEPROM data is invalid. We already have the contents of the SPD EEPROM which are exposed via FPGA I2C accesses, this is provided as part of the SMBUS EEPROM data too for consistency. Signed-off-by: Paul Burton <paul.burton@imgtec.com> Signed-off-by: Leon Alrae <leon.alrae@imgtec.com> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2013-07-28mips_malta: cap BIOS endian swap length at 0x3e0000 bytesPaul Burton1-1/+1
This preserves the final sector of the pflash which is used by YAMON to hold environment variables. If the endianness of the environment data is swapped then YAMON will fail to load environment variables from pflash. Signed-off-by: Paul Burton <paul.burton@imgtec.com> Signed-off-by: Leon Alrae <leon.alrae@imgtec.com> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2013-07-28mips_malta: generate SPD EEPROM data at runtimePaul Burton1-3/+57
The SPD EEPROM specifies the amount of memory present in the system and thus its correct contents can only be known at runtime. Calculating parts of the data on init allows the data to accurately reflect the amount of target memory present and allow YAMON to boot with an arbitrary amount of SDRAM. Where possible the SPD data will favor indicating 2 banks of SDRAM rather than 1. For example the default 128MB of target memory will be represented as 2x64MB banks rather than 1x128MB bank. This allows versions of MIPS BIOS code (such as YAMON 2.22 and older) to boot despite a bug preventing them from handling a single bank of SDRAM with the Galileo GT64120 system controller emulated by QEMU. Signed-off-by: Paul Burton <paul.burton@imgtec.com> Signed-off-by: Leon Alrae <leon.alrae@imgtec.com> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2013-07-28mips_malta: correct reading MIPS revision at 0x1fc00010Paul Burton1-8/+17
Rather than modifying the BIOS code at its original location, copy it for the 0x1fc00000 region & modify the copy. This means the original ROM code is correctly readable at 0x1e000010 whilst the MIPS revision is readable at 0x1fc00010. Additionally the code previously operated on target memory which would later be overwritten by the BIOS image upon CPU reset if the -bios argument was used to specify the BIOS image. This led to the written MIPS revision being lost. Copying using rom_copy when -bios is used fixes this issue. Signed-off-by: Paul Burton <paul.burton@imgtec.com> Signed-off-by: Leon Alrae <leon.alrae@imgtec.com> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2013-07-28mips_malta: fix BIOS endianness swappingPaul Burton1-2/+5
If the target is little endian (mipsel) then the BIOS image endianness is swapped so that the big endian BIOS binaries commonly produced can be loaded correctly. When using the -bios argument the BIOS is loaded using load_image_targphys, however this doesn't perform the load to target memory immediately. Instead it loads the BIOS file into a struct Rom which will later be written to target memory upon reset. However the endianness conversion was being performed before this, on init, and operating on the target memory which at this point is blank & will later be overwritten by the (big endian) BIOS image. Correct this by operating on the data referenced by struct Rom rather than the target memory when the -bios argument is used. Signed-off-by: Paul Burton <paul.burton@imgtec.com> Signed-off-by: Leon Alrae <leon.alrae@imgtec.com> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2013-07-28mips_malta: QOM cast cleanupAndreas Färber1-4/+8
Signed-off-by: Andreas Färber <afaerber@suse.de> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2013-07-25mips: degrade BIOS error to warningPaolo Bonzini4-8/+4
No free MIPS BIOS is available, so it makes little sense to quit. Signed-off-by: Paolo Bonzini <pbonzini@redhat.com> Reviewed-by: Anthony Liguori <aliguori@us.ibm.com> Message-id: 1374501278-31549-19-git-send-email-pbonzini@redhat.com Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
2013-07-25mipssim: do not use isa_mmioPaolo Bonzini1-1/+4
Untested, this board does not support PCI so it cannot run endianness-test. It should fix endianness bugs in I/O port access. Signed-off-by: Paolo Bonzini <pbonzini@redhat.com> Reviewed-by: Anthony Liguori <aliguori@us.ibm.com> Message-id: 1374501278-31549-11-git-send-email-pbonzini@redhat.com Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
2013-07-25mips_malta: do not use isa_mmioPaolo Bonzini1-1/+2
This fixes endianness bugs in I/O port access. Signed-off-by: Paolo Bonzini <pbonzini@redhat.com> Reviewed-by: Anthony Liguori <aliguori@us.ibm.com> Message-id: 1374501278-31549-9-git-send-email-pbonzini@redhat.com Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
2013-07-25mips_r4k: do not use isa_mmioPaolo Bonzini1-1/+5
This fixes endianness bugs in I/O port access. Signed-off-by: Paolo Bonzini <pbonzini@redhat.com> Reviewed-by: Anthony Liguori <aliguori@us.ibm.com> Message-id: 1374501278-31549-8-git-send-email-pbonzini@redhat.com Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
2013-07-25mips_jazz: do not use isa_mmioPaolo Bonzini1-1/+4
This fixes endianness bugs in I/O port access. Signed-off-by: Paolo Bonzini <pbonzini@redhat.com> Reviewed-by: Anthony Liguori <aliguori@us.ibm.com> Message-id: 1374501278-31549-7-git-send-email-pbonzini@redhat.com Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
2013-07-09cpu: Make first_cpu and next_cpu CPUStateAndreas Färber1-1/+2
Move next_cpu from CPU_COMMON to CPUState. Move first_cpu variable to qom/cpu.h. gdbstub needs to use CPUState::env_ptr for now. cpu_copy() no longer needs to save and restore cpu_next. Acked-by: Paolo Bonzini <pbonzini@redhat.com> [AF: Rebased, simplified cpu_copy()] Signed-off-by: Andreas Färber <afaerber@suse.de>
2013-07-09cpu: Replace cpu_single_env with CPUState current_cpuAndreas Färber3-9/+9
Move it to qom/cpu.h. Signed-off-by: Andreas Färber <afaerber@suse.de>
2013-07-08Merge remote-tracking branch 'mst/tags/for_anthony' into stagingAnthony Liguori2-6/+6
pci,misc enhancements This includes some pci enhancements: Better support for systems with multiple PCI root buses FW cfg interface for more robust pci programming in BIOS Minor fixes/cleanups for fw cfg and cross-version migration - because of dependencies with other patches Signed-off-by: Michael S. Tsirkin <mst@redhat.com> # gpg: Signature made Sun 07 Jul 2013 03:11:18 PM CDT using RSA key ID D28D5469 # gpg: Can't check signature: public key not found # By David Gibson (10) and others # Via Michael S. Tsirkin * mst/tags/for_anthony: pci: Fold host_buses list into PCIHostState functionality pci: Remove domain from PCIHostBus pci: Simpler implementation of primary PCI bus pci: Add root bus parameter to pci_nic_init() pci: Add root bus argument to pci_get_bus_devfn() pci: Replace pci_find_domain() with more general pci_root_bus_path() pci: Use helper to find device's root bus in pci_find_domain() pci: Abolish pci_find_root_bus() pci: Move pci_read_devaddr to pci-hotplug-old.c pci: Cleanup configuration for pci-hotplug.c pvpanic: fix fwcfg for big endian hosts pvpanic: initialization cleanup MAINTAINERS: s/Marcelo/Paolo/ e1000: cleanup process_tx_desc pc_piix: cleanup init compat handling pc: pass PCI hole ranges to Guests pci: store PCI hole ranges in guestinfo structure range: add Range structure Message-id: 1373228271-31223-1-git-send-email-mst@redhat.com Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
2013-07-07pci: Add root bus parameter to pci_nic_init()David Gibson2-6/+6
At present, pci_nic_init() and pci_nic_init_nofail() assume that they will only create a NIC under the primary PCI root. As we add support for multiple PCI roots, that may no longer be the case. This patch adds a root bus parameter to pci_nic_init() (and updates callers accordingly) to allow the machine init code using it to specify the right PCI root for NICs created by old-style -net nic parameters. NICs created new-style, with -device can of course be put anywhere. Signed-off-by: David Gibson <david@gibson.dropbear.id.au> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
2013-07-04hw/m*: pass owner to memory_region_init* functionsPaolo Bonzini1-1/+1
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2013-07-04memory: add owner argument to initialization functionsPaolo Bonzini6-19/+19
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2013-06-28cpu: Change cpu_exit() argument to CPUStateAndreas Färber3-3/+3
It no longer depends on CPUArchState, so move it to qom/cpu.c. Prepares for changing GDBState::c_cpu to CPUState. Signed-off-by: Andreas Färber <afaerber@suse.de>
2013-05-18remove some double-includesMichael Tokarev1-1/+0
Some source files #include the same header more than once for no good reason. Remove second #includes in such cases. Signed-off-by: Michael Tokarev <mjt@tls.msk.ru>
2013-04-29audio: enable PCI audio cards for all PCI-enabled targetsPaolo Bonzini2-5/+0
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com> Message-id: 1366303444-24620-9-git-send-email-pbonzini@redhat.com Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
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