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2013-02-12hw/m25p80.c: add WRSR(0x01) supportKuo-Jung Su1-0/+15
Atmel, SST and Intel/Numonyx serial flash tend to power up with the software protection bits set. And thus the new m25p80.c in linux kernel would always tries to use WREN(0x06) + WRSR(0x01) to turn-off the protection. The WEL(0x02) of status register is supposed to be cleared after WRSR(0x01). There are also some drivers (i.e mine for RTOSes) would check the WEL(0x02) in status register to make sure the protection is correctly turned off. Signed-off-by: Kuo-Jung Su <dantesu@faraday-tech.com> Cc: Peter Crosthwaite <peter.crosthwaite@xilinx.com> Cc: Peter Maydell <peter.maydell@linaro.org> Cc: Edgar E. Iglesias <edgar.iglesias@gmail.com> Reviewed-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com> Signed-off-by: Edgar E. Iglesias <edgar.iglesias@gmail.com>
2013-01-27m25p80.c: Return state to IDLE after COLLECTINGPeter Crosthwaite1-0/+2
Default to moving back to the IDLE state after the COLLECTING_DATA state. For a well behaved guest this patch has no consequence, but A bad guest could crash QEMU by using one of the erase commands followed by a longer than 5 byte argument (undefined behaviour). Signed-off-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com> Signed-off-by: Edgar E. Iglesias <edgar.iglesias@gmail.com>
2012-12-19softmmu: move include files to include/sysemu/Paolo Bonzini1-1/+1
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2012-10-29m25p80: Support for Quad SPIPeter Crosthwaite1-4/+57
Added the Quad mode read and write commands. Data remains serialized on a single wire, i.e. the quad mode instructions just behave the same as single mode, with the expection of modelling the varying number of dummy/mode bytes between the address bytes and the first data word. Signed-off-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com>
2012-10-10m25p80: Initial implementation of SPI flash devicePeter A. G. Crosthwaite1-0/+598
Added device model for m25p80 style SPI flash family. Signed-off-by: Peter A. G. Crosthwaite <peter.crosthwaite@petalogix.com>