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2014-09-12Merge remote-tracking branch 'remotes/bonzini/tags/for-upstream' into stagingPeter Maydell22-44/+74
- Memory: improve error reporting and avoid crashes on hotplug - Build: fixing block/iscsi.so and ranlib warnings on Mac OS X - Migration fixes for x86 - The odd KVM patch. # gpg: Signature made Thu 11 Sep 2014 11:21:10 BST using RSA key ID 9B4D86F2 # gpg: Good signature from "Paolo Bonzini <pbonzini@redhat.com>" # gpg: aka "Paolo Bonzini <bonzini@gnu.org>" * remotes/bonzini/tags/for-upstream: (21 commits) gdbstub: init mon_chr through qemu_chr_alloc pckbd: adding new fields to vmstate mc146818rtc: add missed field to vmstate piix: do not set irq while loading vmstate serial: fixing vmstate for save/restore parallel: adding vmstate for save/restore fdc: adding vmstate for save/restore cpu: init vmstate for ticks and clock offset apic_common: vapic_paddr synchronization fix vl: use QLIST_FOREACH_SAFE to visit change state handlers exec: add parameter errp to gethugepagesize exec: report error when memory < hpagesize hostmem-ram: don't exit qemu if size of memory-backend-ram is way too big memory: add parameter errp to memory_region_init_rom_device memory: add parameter errp to memory_region_init_ram exec: add parameter errp to qemu_ram_alloc and qemu_ram_alloc_from_ptr rules.mak: Fix DSO build by pulling in archive symbols util: Don't link host-utils.o if it's empty util: Move general qemu_getauxval to util/getauxval.c trace: Only link generated-tracers.o with "simple" backend ... Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2014-09-12hw/arm/boot: enable DTB support when booting ELF imagesArd Biesheuvel1-2/+20
Add support for loading DTB images when booting ELF images using -kernel. If there are no conflicts with the placement of the ELF segments, the DTB image is loaded at the base of RAM. Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Message-id: 1410453915-9344-5-git-send-email-ard.biesheuvel@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2014-09-12hw/arm/boot: load device tree to base of DRAM if no -kernel option was passedArd Biesheuvel1-0/+10
If we are running the 'virt' machine, we may have a device tree blob but no kernel to supply it to if no -kernel option was passed. In that case, copy it to the base of RAM where it can be picked up by a bootloader. Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Message-id: 1410453915-9344-4-git-send-email-ard.biesheuvel@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2014-09-12hw/arm/boot: pass an address limit to and return size from load_dtb()Ard Biesheuvel1-3/+31
Add an address limit input parameter to load_dtb() so that we can tell load_dtb() how much memory the dtb is allowed to consume. If the dtb doesn't fit, return 0, otherwise return the actual size of the loaded dtb. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Message-id: 1410453915-9344-3-git-send-email-ard.biesheuvel@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2014-09-12hw/arm/boot: load DTB as a ROM imageArd Biesheuvel1-1/+4
In order to make the device tree blob (DTB) available in memory not only at first boot, but also after system reset, use rom_blob_add_fixed() to install it into memory. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Message-id: 1410453915-9344-2-git-send-email-ard.biesheuvel@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2014-09-12hw/arm/virt: fix pl011 and pl031 irq flagsPeter Maydell1-2/+2
The pl011 and pl031 devices both use level triggered interrupts, but the device tree we construct was incorrectly telling the kernel to configure the GIC to treat them as edge triggered. This meant that output from the pl011 would hang after a while. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 1410274423-9461-1-git-send-email-peter.maydell@linaro.org Acked-by: Christoffer Dall <christoffer.dall@linaro.org> Cc: qemu-stable@nongnu.org
2014-09-12hw/arm/virt: Provide flash devices for boot ROMsPeter Maydell1-0/+70
Add two flash devices to the virt board, so that it can be used for running guests which want a bootrom image such as UEFI. We provide two flash devices to make it more convenient to provide both a read-only UEFI image and a read-write place to store guest-set UEFI config variables. The '-bios' command line option is set up to provide an image for the first of the two flash devices. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Paolo Bonzini <pbonzini@redhat.com> Message-id: 1409930126-28449-2-git-send-email-ard.biesheuvel@linaro.org
2014-09-12hw/arm/virt: add linux, stdout-path to /chosen DT nodeArd Biesheuvel1-0/+2
Add a property "linux,stdout-path" to the /chosen DT node and make it point to the emulated UART. This allows users such as the Linux kernel to produce console output without the need to pass console= or earlycon=pl011,0x... command line arguments. Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Message-id: 1409317439-29349-1-git-send-email-ard.biesheuvel@linaro.org Reviewed-by: Rob Herring <rob.herring@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2014-09-09memory: add parameter errp to memory_region_init_ramHu Tao22-44/+74
Add parameter errp to memory_region_init_ram and update all call sites to pass in &error_abort. Signed-off-by: Hu Tao <hutao@cn.fujitsu.com> Reviewed-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2014-08-29aarch64: raise max_cpus to 8Joel Schopp1-1/+1
I'm running on a system with 8 cpus and it would be nice to have qemu support all of them. The attached patch does that and has been tested. That said, I'm not sure if 8 is enough or if we want to bump this even higher now before systems with many more cpus come along. 255 anyone? Cc: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Joel Schopp <joel.schopp@amd.com> Message-id: 20140819213304.19537.2834.stgit@joelaarch64.amd.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2014-08-19arm: stellaris: Remove misleading address_space_mem varPeter Crosthwaite1-2/+1
It's a MemoryRegion and not an AddressSpace. But since it's single use, just inline the get_system_memory() call to the only usage to remove it. Signed-off-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com> Message-id: d6914047e10b956514cfaa5f391ef56c7d851b34.1408347860.git.peter.crosthwaite@xilinx.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2014-08-19arm: armv7m: Rename address_space_mem -> system_memoryPeter Crosthwaite1-4/+4
This argument is a MemoryRegion and not an AddressSpace. "Address space" means something quite different to "memory region" in QEMU parlance so rename the variable to reduce confusion. Signed-off-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com> Message-id: f666cf7f2318d9b461b1e320a45bf0d82da9b7dd.1408347860.git.peter.crosthwaite@xilinx.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2014-08-19aarch64: Allow -kernel option to take a gzip-compressed kernel.Richard W.M. Jones1-0/+7
On aarch64 it is the bootloader's job to uncompress the kernel. UEFI and u-boot bootloaders do this automatically when the kernel is gzip-compressed. However the qemu -kernel option does not do this. The following command does not work: qemu-system-aarch64 [...] -kernel /boot/vmlinuz because it tries to execute the gzip-compressed data. This commit lets gzip-compressed kernels be uncompressed transparently. Currently this is only done when emulating aarch64. Signed-off-by: Richard W.M. Jones <rjones@redhat.com> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Message-id: 1407831259-2115-3-git-send-email-rjones@redhat.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2014-08-19arm/virt: Use PSCI v0.2 function IDs in the DT when KVM uses PSCI v0.2Christoffer Dall1-5/+26
The current code supplies the PSCI v0.1 function IDs in the DT even when KVM uses PSCI v0.2. This will break guest kernels that only support PSCI v0.1 as they will use the IDs provided in the DT. Guest kernels with PSCI v0.2 support are not affected by this patch, because they ignore the function IDs in the device tree and rely on the architecture definition. Define QEMU versions of the constants and check that they correspond to the Linux defines on Linux build hosts. After this patch, both guest kernels with PSCI v0.1 support and guest kernels with PSCI v0.2 should work. Tested on TC2 for 32-bit and APM Mustang for 64-bit (aarch64 guest only). Both cases tested with 3.14 and linus/master and verified I could bring up 2 cpus with both guest kernels. Also tested 32-bit with a 3.14 host kernel with only PSCI v0.1 and both guests booted here as well. Cc: qemu-stable@nongnu.org Signed-off-by: Christoffer Dall <christoffer.dall@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2014-08-19target-arm: Rename QEMU PSCI v0.1 definitionsChristoffer Dall1-4/+4
The function IDs for PSCI v0.1 are exported by KVM and defined as KVM_PSCI_FN_<something>. To build using these defines in non-KVM code, QEMU defines these IDs locally and check their correctness against the KVM headers when those are available. However, the naming scheme used for QEMU (almost) clashes with the PSCI v0.2 definitions from Linux so to avoid unfortunate naming when we introduce local PSCI v0.2 defines, rename the current local defines with QEMU_ prependend and clearly identify the PSCI version as v0.1 in the defines. Cc: qemu-stable@nongnu.org Signed-off-by: Christoffer Dall <christoffer.dall@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2014-08-04hw/arm/virt: formatting: memory mapAndrew Jones1-8/+8
Add some spacing and zeros to make it easier to read and modify the map. This patch has no functional changes. The review looks ugly, but it's actually pretty easy to confirm all the addresses are as they should be - thanks to the new formatting ;-) Signed-off-by: Andrew Jones <drjones@redhat.com> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2014-08-04hw/arm/boot: Set PC correctly when loading AArch64 ELF filesPeter Maydell1-2/+6
The code in do_cpu_reset() correctly handled AArch64 CPUs when running Linux kernels, but was missing code in the branch of the if() that deals with loading ELF files. Correctly jump to the ELF entry point on reset rather than leaving the reset PC at zero. Reported-by: Christopher Covington <cov@codeaurora.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Tested-by: Christopher Covington <cov@codeaurora.org> Cc: qemu-stable@nongnu.org
2014-07-29hw/arm/virt: fix pl031 addr typoAndrew Jones1-1/+1
pl031's base address should be 0x9010000, not 0x90010000, otherwise it sits in ram when configuring a guest with greater than 1G. Signed-off-by: Andrew Jones <drjones@redhat.com> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2014-07-08hw/arm/vexpress: Alias NOR flash at 0 for vexpress-a9Peter Maydell1-1/+1
Make the vexpress-a9 board alias the first NOR flash region at address zero, like vexpress-a15. This makes "-bios" actually usable on this board. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 1404310070-3561-1-git-send-email-peter.maydell@linaro.org Reviewed-by: Greg Bellows <greg.bellows@linaro.org>
2014-06-30hw: Fix qemu_allocate_irqs() leaksAndreas Färber5-13/+13
Replace qemu_allocate_irqs(foo, bar, 1)[0] with qemu_allocate_irq(foo, bar, 0). This avoids leaking the dereferenced qemu_irq *. Cc: Markus Armbruster <armbru@redhat.com> Reviewed-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Andreas Färber <afaerber@suse.de> [PC Changes: * Applied change to instance in sh4/sh7750.c ] Signed-off-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com> Reviewed-by: Kirill Batuzov <batuzovk@ispras.ru> [AF: Fix IRQ index in sh4/sh7750.c] Cc: qemu-stable@nongnu.org Signed-off-by: Andreas Färber <afaerber@suse.de>
2014-06-29hw/arm/pxa2xx_gpio: Correct and register vmstatePeter Maydell1-1/+2
The pxa2xx-gpio device has a VMStateDescription, but it was accidentally never actually registered, and it wasn't quite correct. Remove the 'lines' field (this is a device property, not mutable state), add the missing 'prev_level' field, and set dc->vmsd so it actually gets used. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com>
2014-06-29hw/arm/pxa2xx_gpio: Fix handling of GPSR/GPCR readsPeter Maydell1-8/+6
The PXA2xx GPIO GPSR and GPCR registers are write-only, with reads being undefined behaviour. Instead of having GPCR return 31337 and GPSR return the value last written, make both log the guest error and return 0. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com>
2014-06-29hw/arm/strongarm: Wire up missing GPIO and PPC vmstatePeter Maydell1-0/+4
The VMStateDescription structs for the GPIO and PPC devices were accidentally never wired up. Add missing state fields and register them via dc->vmsd. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com>
2014-06-29hw/arm/strongarm: Fix handling of GPSR/GPCR readsPeter Maydell1-8/+6
The StrongARM GPIO GPSR and GPCR registers are write-only, with reads being undefined behaviour. Instead of having GPCR return 31337 and GPSR return the value last written, make both log the guest error and return 0. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com>
2014-06-29hw/arm/virt: Provide PL031 RTCPeter Maydell1-0/+30
UEFI mandates that the platform must include an RTC, so provide one in 'virt', using the PL031. This is also useful for directly booting Linux kernels which would otherwise have to run ntpdate. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Tested-by: Aurelien Jarno <aurelien@aurel32.net> Reviewed-by: Aurelien Jarno <aurelien@aurel32.net>
2014-06-19Use PSCI v0.2 compatible string when KVM or TCG provides itPranavkumar Sawargaonkar1-1/+15
If we have PSCI v0.2 emulation available for KVM ARM/ARM64 or TCG then we need to provide PSCI v0.2 compatible string via generated DTB. Signed-off-by: Pranavkumar Sawargaonkar <pranavkumar@linaro.org> Signed-off-by: Anup Patel <anup.patel@linaro.org> Reviewed-by: Rob Herring <rob.herring@linaro.org> Message-id: 1402901605-24551-9-git-send-email-pranavkumar@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2014-06-19hw/arm/vexpress: Forbid specifying flash contents in two ways at oncePeter Maydell1-1/+9
Detect attempts by the user to specify the contents of the first flash device via both -bios and -drive if=pflash... simultaneously and print a helpful error message. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 1402419834-25982-1-git-send-email-peter.maydell@linaro.org
2014-06-19hw/arm/spitz: Avoid clash with Windows header symbol MOD_SHIFTPeter Maydell1-50/+58
The Windows headers provided by MinGW define MOD_SHIFT. Avoid it by using SPITZ_MOD_* for our constants here. Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2014-06-09vexpress: Add support for the -bios flag to provide firmwareGrant Likely1-0/+13
Right now to run firmware inside the QEMU VExpress model requires padding out the firmware image to the size of the virtual flash and passing it in via the -pflash argument. If the firmware image is passed without padding, then QEMU will fail. Also, when passed as a -pflash argument, QEMU treats the file as persistent storage and will modify the file. The -bios flag provides the semantics that we want for providing a firmware image. This patch maps the contents of the -bios file into the address space at the boot flash location. Tested with the vexpress-a15 model and the Tianocore port. Signed-off-by: Grant Likely <grant.likely@linaro.org> Tested-by: Roy Franz <roy.franz@linaro.org> [PMM: folded long line, removed stray \n from error message, use correct variable for printing image name, exit(1) rather than 0] Reviewed-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2014-06-05hw: use ld_p/st_p instead of ld_raw/st_rawPaolo Bonzini1-118/+118
The ld_raw and st_raw definitions are only needed in code that must compile for both user-mode and softmmu emulation. Device models can use the equivalent ld_p/st_p which are simple pointer accessors. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2014-06-05nseries: clean up coding stylePaolo Bonzini1-127/+145
Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2014-05-28ssi: Name the CS GPIOPeter Crosthwaite2-4/+5
To get it out of the default GPIO list. This allows child devices to use the un-named GPIO namespace without having to be SSI aware. That is, there is no more need for machines to know about the obscure policy where GPIO 0 is the SSI chip-select and GPIO 1..N are the concrete class GPIOs (defined locally as 0..N-1). This is most notable in stellaris, which uses a device which has both SSI and concrete level GPIOs. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com> Signed-off-by: Andreas Färber <afaerber@suse.de>
2014-05-28machine: Conversion of QEMUMachineInitArgs to MachineStateMarcel Apfelbaum22-175/+178
Total removal of QEMUMachineInitArgs struct. QEMUMachineInitArgs's fields are copied into MachineState. Removed duplicated fields from MachineState. All the other changes are only mechanical refactoring, no semantic changes. Signed-off-by: Marcel Apfelbaum <marcel.a@redhat.com> Acked-by: Cornelia Huck <cornelia.huck@de.ibm.com> (s390) Reviewed-by: Michael S. Tsirkin <mst@redhat.com> (PC) [AF: Renamed ms -> machine, use MACHINE_GET_CLASS()] Signed-off-by: Andreas Färber <afaerber@suse.de>
2014-05-13hw/arm/stellaris: Correct handling of GPTM TAR registerPeter Maydell1-3/+10
We don't implement very much of the GPTM TAR register, and what we do is wrong. The "are we in RT mode?" field is in s->config, not s->control. Correct this, use LOG_UNIMP rather than hw_error() for the cases we don't support, and avoid an unlabelled fallthrough that makes Coverity complain. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com>
2014-05-13hw/arm/omap1: Avoid unintended sign extension writing omap_rtc YEARS_REGPeter Maydell1-2/+2
When writing to the YEARS_REG register, if the year value is 99 then the multiplication by 31536000 will overflow into the sign bit of a 32 bit value and then be erroneously sign-extended if time_t is 64 bits. Add a cast to avoid this. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com>
2014-05-13savevm: Remove all the unneeded version_minimum_id_old (arm)Juan Quintela9-49/+15
After commit 767adce2d, they are redundant. This way we don't assign them except when needed. Once there, there were lots of cases where the ".fields" indentation was wrong: .fields = (VMStateField []) { and .fields = (VMStateField []) { Change all the combinations to: .fields = (VMStateField[]){ The biggest problem (apart from aesthetics) was that checkpatch complained when we copy&pasted the code from one place to another. Signed-off-by: Juan Quintela <quintela@redhat.com> [PMM: fixed minor conflict, corrected commit message typos] Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2014-05-05pxa2xx: avoid buffer overrun on incoming migrationMichael S. Tsirkin1-2/+6
CVE-2013-4533 s->rx_level is read from the wire and used to determine how many bytes to subsequently read into s->rx_fifo[]. If s->rx_level exceeds the length of s->rx_fifo[] the buffer can be overrun with arbitrary data from the wire. Fix this by validating rx_level against the size of s->rx_fifo. Cc: Don Koch <dkoch@verizon.com> Reported-by: Michael Roth <mdroth@linux.vnet.ibm.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Don Koch <dkoch@verizon.com> Signed-off-by: Juan Quintela <quintela@redhat.com>
2014-05-01hw/arm/virt: Add support for Cortex-A57Peter Maydell1-0/+5
Support the Cortex-A57 in the virt machine model. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 1398362083-17737-4-git-send-email-peter.maydell@linaro.org
2014-05-01hw/arm/virt: Put GIC register banks on 64K boundariesPeter Maydell1-3/+3
For an AArch64 CPU which supports 64K pages, having the GIC register banks at 4K offsets is potentially awkward. Move them out to being at 64K offsets. (This is harmless for AArch32 CPUs and for AArch64 CPUs with 4K pages, so it is simpler to use the same offsets everywhere than to try to use 64K offsets only for AArch64 host CPUs.) Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 1398362083-17737-3-git-send-email-peter.maydell@linaro.org
2014-05-01hw/arm/virt: Create the GIC ourselves rather than (ab)using a15mpcore_privPeter Maydell1-29/+53
Rather than having the virt machine model create an a15mpcore_priv device regardless of the actual CPU type in order to instantiate the GIC, move to having the machine model create the GIC directly. This corresponds to a system which uses a standalone GIC (eg the GIC-400) rather than the one built in to the CPU core. The primary motivation for this is to support the Cortex-A57, which for a KVM configuration will use a GICv2, which is not built into the CPU. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 1398362083-17737-2-git-send-email-peter.maydell@linaro.org
2014-04-17allwinner-a10-pit: implement prescaler and source selectionBeniamino Galvani1-0/+13
This implements the prescaler and source fields of the timer control register. The source for each timer can be selected among 4 clock inputs whose frequencies are set through model properties. Signed-off-by: Beniamino Galvani <b.galvani@gmail.com> Reviewed-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com> Message-id: 1395771730-16882-6-git-send-email-b.galvani@gmail.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2014-04-04hw/arm/vexpress, hw/arm/highbank: Don't insist that CPU has reset-cbar propertyPeter Maydell2-11/+10
For the machine models which can have a Cortex-A15 CPU (vexpress-a15 and midway), silently continue if the CPU object has no reset-cbar property rather than failing. This allows these boards to be used under KVM with the "-cpu host" option, since the 'host' CPU object has no reset-cbar property. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Rob Herring <rob.herring@linaro.org>
2014-04-04hw/arm/highbank: Don't segfault on unknown CPU namesPeter Maydell1-0/+5
If the user passes an unknown CPU name via the '-cpu' option, exit with an error message rather than segfaulting. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Rob Herring <rob.herring@linaro.org>
2014-03-27hw/arm: Stop specifying integratorcp as the default boardPeter Maydell1-1/+0
Currently for both qemu-system-arm and qemu-system-aarch64 the default board model if the user doesn't specify one is the 'integratorcp'. This is a totally arbitrary historical accident since it was the first board to be modelled. That board is now just one target among many for us, and is a very poor choice of default: * it's an ancient board that is now only found in the junkpiles of longtime ARM/Linux hackers, if at all * it's an ARMv5 CPU, when most distros are now assuming ARMv7 * it's pretty much unmaintained in QEMU * it doesn't even have versatilepb's advantage of supporting PCI Making it or any other board the default serves only to confuse people new to ARM who expect something more like the x86 monoculture. Remove the is_default marker from integratorcp, and don't set it for any other board, to give users a nudge that they need to think about which board they want a QEMU model of. (QEMU will produce the admittedly slightly cryptic error "No machine found.") Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Paolo Bonzini <pbonzini@redhat.com>
2014-03-24target-arm: Load ELF images with the correct machine type for CPUPeter Maydell1-1/+4
When trying to load an ELF file specified via -kernel, we need to pass load_elf() the ELF machine type corresponding to the CPU we're booting with, not the one corresponding to the softmmu binary we happen to be running. (The two are different in the case of loading a 32-bit ARM ELF file into a 32 bit CPU being emulated by qemu-system aarch64.) This was causing us to incorrectly fail to load ELF images in this situation. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Andreas Färber <afaerber@suse.de> Message-id: 1395427476-25546-1-git-send-email-peter.maydell@linaro.org
2014-03-17virt: Set reset-cbar on CPUsPeter Maydell1-0/+6
Set the reset-cbar property on CPUs used by the virt board, if they have it. This isn't necessary for correct functioning under Linux (since the A9 isn't a valid CPU for the virt board), but it is the correct behaviour. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com> Message-id: 1394462692-8871-5-git-send-email-peter.maydell@linaro.org
2014-03-17exynos4210: Set reset-cbar property of Cortex-A9 CPUsPeter Maydell1-3/+13
Set the reset-cbar property of the Exynos4210 SoC's Cortex-A9 CPUs, so that Linux doesn't misrecognize them as a broken uniprocessor SoC. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com> Message-id: 1394462692-8871-4-git-send-email-peter.maydell@linaro.org
2014-03-17realview-pbx-a9: Set reset-cbar property for CPUsPeter Maydell1-10/+29
If the CPU is a Cortex-A9 then we should set its reset-cbar property so that the guest can read the correct PERIPHBASE/CBAR register value; newer versions of the Linux kernel (as of commit bc41b8724 in 3.12) will otherwise assume the CPU is a buggy single core A9 SoC. The realview-pbx-a9 is the only one of the cluster of boards in realview.c which works with the Cortex-A9 (ie which gets an a9mpcore_priv device); make sure it also has reset-cbar set correctly. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com> Message-id: 1394462692-8871-3-git-send-email-peter.maydell@linaro.org
2014-03-17vexpress: Set reset-cbar property for CPUsPeter Maydell1-62/+61
Newer versions of the Linux kernel (as of commit bc41b8724 in 3.12) now assume that if the CPU is a Cortex-A9 and the reset value of the PERIPHBASE/CBAR register is zero then the CPU is a specific buggy single core A9 SoC, and will not try to start other cores. Since we now have a CPU property for the reset value of the CBAR, we can just fix the vexpress board model to correctly set CBAR so SMP works again. To avoid duplicate boilerplate code in both the A9 and A15 daughterboard init functions, we split out the CPU and private memory region init to its own function. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reported-by: Rob Herring <rob.herring@linaro.org> Reviewed-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com> Message-id: 1394462692-8871-2-git-send-email-peter.maydell@linaro.org
2014-03-12ssi: Convert legacy SSI_SLAVE -> DEVICE castsPeter Crosthwaite1-6/+7
Convert legacy ->qdev style casts from TYPE_SSI_SLAVE to TYPE_DEVICE. Signed-off-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com> [AF: Introduce local DeviceState variable for transition to QOM realize] Signed-off-by: Andreas Färber <afaerber@suse.de>
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