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2014-09-01pc-bios/s390-ccw Really big EAV ECKD DASD handlingEugene (jno) Dvurechenski3-22/+22
For EAV ECKD DASD, the cylinder count will have the magic value 0xfffeU. Therefore, use the block number to test for valid eckd addresses instead. Signed-off-by: Eugene (jno) Dvurechenski <jno@linux.vnet.ibm.com> Acked-by: Cornelia Huck <cornelia.huck@de.ibm.com> Acked-by: Christian Borntraeger <borntraeger@de.ibm.com> Reviewed-by: David Hildenbrand <dahi@linux.vnet.ibm.com> Signed-off-by: Jens Freimann <jfrei@linux.vnet.ibm.com> Signed-off-by: Christian Borntraeger <borntraeger@de.ibm.com>
2014-09-01pc-bios/s390-ccw Improve ECKD informational messageEugene (jno) Dvurechenski1-2/+20
Add block size display to ECKD scheme report. Signed-off-by: Eugene (jno) Dvurechenski <jno@linux.vnet.ibm.com> Reviewed-by: David Hildenbrand <dahi@linux.vnet.ibm.com> Acked-by: Christian Borntraeger <borntraeger@de.ibm.com> Acked-by: Cornelia Huck <cornelia.huck@de.ibm.com> Signed-off-by: Jens Freimann <jfrei@linux.vnet.ibm.com> Signed-off-by: Christian Borntraeger <borntraeger@de.ibm.com>
2014-09-01pc-bios/s390-ccw: handle more ECKD DASD block sizesEugene (jno) Dvurechenski1-3/+24
Using dasdfmt(8) to format a DASD allows to choose a block size. There are four supported values: 512, 1024, 2048, and 4096 bytes per block. Each block size leads to selection of new count of sectors per track. The head count remains always the same: 15. This empiric knowledge is used to detect ECKD DASD to IPL from. Signed-off-by: Eugene (jno) Dvurechenski <jno@linux.vnet.ibm.com> Reviewed-by: David Hildenbrand <dahi@linux.vnet.ibm.com> Acked-by: Christian Borntraeger <borntraeger@de.ibm.com> Signed-off-by: Jens Freimann <jfrei@linux.vnet.ibm.com> Signed-off-by: Christian Borntraeger <borntraeger@de.ibm.com>
2014-09-01pc-bios/s390-ccw: support all virtio block sizeEugene (jno) Dvurechenski1-6/+8
The block size value may be given "as is" OR as a base value and a shift count (exponent). So, we have to use calculation to get the proper number in the code. The main expression reads as (blk_cfg.blk_size << blk_cfg.physical_block_exp) E.g., various combinations between blk_size=1/physical_block_exp=12 and blk_size=4096/physical_block_exp=0 are valid for 4K blocks. Signed-off-by: Eugene (jno) Dvurechenski <jno@linux.vnet.ibm.com> Acked-by: Christian Borntraeger <borntraeger@de.ibm.com> Reviewed-by: David Hildenbrand <dahi@linux.vnet.ibm.com> Signed-off-by: Jens Freimann <jfrei@linux.vnet.ibm.com> Signed-off-by: Christian Borntraeger <borntraeger@de.ibm.com>
2014-09-01s390x/kvm: execute the first cpu reset on the vcpu threadDavid Hildenbrand1-0/+4
As all full cpu resets currently call into the kernel to do initial cpu reset, let's run this reset (triggered by cpu_s390x_init()) on the proper vcpu thread. Reviewed-by: Cornelia Huck <cornelia.huck@de.ibm.com> Acked-by: Christian Borntraeger <borntraeger@de.ibm.com> Signed-off-by: David Hildenbrand <dahi@linux.vnet.ibm.com> Signed-off-by: Jens Freimann <jfrei@linux.vnet.ibm.com> Signed-off-by: Christian Borntraeger <borntraeger@de.ibm.com>
2014-09-01s390x/kvm: execute "system reset" cpu resets on the vcpu threadDavid Hildenbrand1-1/+1
Let's execute resets triggered by qemu system resets on the target vcpu thread. This will avoid synchronize_rcu's in the kernel. Reviewed-by: Cornelia Huck <cornelia.huck@de.ibm.com> Acked-by: Christian Borntraeger <borntraeger@de.ibm.com> Signed-off-by: David Hildenbrand <dahi@linux.vnet.ibm.com> Signed-off-by: Jens Freimann <jfrei@linux.vnet.ibm.com> Signed-off-by: Christian Borntraeger <borntraeger@de.ibm.com>
2014-09-01s390x/kvm: execute sigp orders on the target vcpu threadDavid Hildenbrand1-7/+16
All sigp orders that can result in ioctls on the target vcpu should be executed on the associated vcpu thread. Reviewed-by: Cornelia Huck <cornelia.huck@de.ibm.com> Acked-by: Christian Borntraeger <borntraeger@de.ibm.com> Signed-off-by: David Hildenbrand <dahi@linux.vnet.ibm.com> Signed-off-by: Jens Freimann <jfrei@linux.vnet.ibm.com> Signed-off-by: Christian Borntraeger <borntraeger@de.ibm.com>
2014-09-01s390x/kvm: run guest triggered resets on the target vcpu threadDavid Hildenbrand2-22/+23
Currently, load_normal_reset() and modified_clear_reset() as triggered by a guest vcpu will initiate cpu resets on the current vcpu thread for all cpus. The reset should happen on the individual vcpu thread instead, so let's use run_on_cpu() for this. This avoids calls to synchronize_rcu() in the kernel. Reviewed-by: Cornelia Huck <cornelia.huck@de.ibm.com> Acked-by: Christian Borntraeger <borntraeger@de.ibm.com> Signed-off-by: David Hildenbrand <dahi@linux.vnet.ibm.com> Signed-off-by: Jens Freimann <jfrei@linux.vnet.ibm.com> Signed-off-by: Christian Borntraeger <borntraeger@de.ibm.com>
2014-08-29Merge remote-tracking branch ↵Peter Maydell19-143/+697
'remotes/pmaydell/tags/pull-target-arm-20140829' into staging target-arm queue: * support PMCCNTR in ARMv8 * various GIC fixes and cleanups * Correct Cortex-A57 ISAR5 and AA64ISAR0 ID register values * Fix regression that disabled VFP for ARMv5 CPUs * Update to upstream VIXL 1.5 # gpg: Signature made Fri 29 Aug 2014 15:34:47 BST using RSA key ID 14360CDE # gpg: Good signature from "Peter Maydell <peter.maydell@linaro.org>" * remotes/pmaydell/tags/pull-target-arm-20140829: target-arm: Implement pmccfiltr_write function target-arm: Remove old code and replace with new functions target-arm: Implement pmccntr_sync function target-arm: Add arm_ccnt_enabled function target-arm: Implement PMCCNTR_EL0 and related registers arm: Implement PMCCNTR 32b read-modify-write target-arm: Make the ARM PMCCNTR register 64-bit hw/intc/arm_gic: honor target mask in gic_update() aarch64: raise max_cpus to 8 arm_gic: Use GIC_NR_SGIS constant arm_gic: Do not force PPIs to edge-triggered mode arm_gic: GICD_ICFGR: Write model only for pre v1 GICs arm_gic: Fix read of GICD_ICFGR target-arm: Correct Cortex-A57 ISAR5 and AA64ISAR0 ID register values target-arm: Fix regression that disabled VFP for ARMv5 CPUs disas/libvixl: Update to upstream VIXL 1.5 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2014-08-29target-arm: Implement pmccfiltr_write functionAlistair Francis1-0/+9
This is the function that is called when writing to the PMCCFILTR_EL0 register Signed-off-by: Alistair Francis <alistair.francis@xilinx.com> Signed-off-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com> Message-id: 73da3da6404855b17d5ae82975a32ff3a4dcae3d.1409025949.git.peter.crosthwaite@xilinx.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2014-08-29target-arm: Remove old code and replace with new functionsAlistair Francis1-23/+4
Remove the old PMCCNTR code and replace it with calls to the new pmccntr_sync() and arm_ccnt_enabled() functions. Signed-off-by: Alistair Francis <alistair.francis@xilinx.com> Signed-off-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com> Message-id: 693a6e437d915c2195fd3dc7303f384ca538b7bf.1409025949.git.peter.crosthwaite@xilinx.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2014-08-29target-arm: Implement pmccntr_sync functionAlistair Francis2-0/+34
This is used to synchronise the PMCCNTR counter and swap its state between enabled and disabled if required. It must always be called twice, both before and after any logic that could change the state of the PMCCNTR counter. Signed-off-by: Alistair Francis <alistair.francis@xilinx.com> Signed-off-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com> Message-id: 62811d4c0f7b1384f7aab62ea2fcfda3dcb0db50.1409025949.git.peter.crosthwaite@xilinx.com [PMM: fixed minor typos in pmccntr_sync doc comment] Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2014-08-29target-arm: Add arm_ccnt_enabled functionAlistair Francis1-0/+12
Include a helper function to determine if the CCNT counter is enabled. Signed-off-by: Alistair Francis <alistair.francis@xilinx.com> Signed-off-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com> Message-id: e1a64f17a756e06c8bda8238ad4826d705049f7a.1409025949.git.peter.crosthwaite@xilinx.com [ PC changes * Remove EL based checks ] Signed-off-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2014-08-29target-arm: Implement PMCCNTR_EL0 and related registersAlistair Francis2-8/+42
This patch adds support for the ARMv8 version of the PMCCNTR and related registers. It also starts to implement the PMCCFILTR_EL0 register. Signed-off-by: Alistair Francis <alistair.francis@xilinx.com> Signed-off-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com> Message-id: b5d1094764a5416363ee95216799b394ecd011e8.1409025949.git.peter.crosthwaite@xilinx.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2014-08-29arm: Implement PMCCNTR 32b read-modify-writePeter Crosthwaite1-1/+10
The register is now 64bit, however a 32 bit write to the register should leave the higher bits unchanged. The open coded write handler does not implement this, so we need to read-modify-write accordingly. Signed-off-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com> Reviewed-by: Alistair Francis <alistair23@gmail.com> Message-id: ec350573424bb2adc1701c3b9278d26598e2f2d1.1409025949.git.peter.crosthwaite@xilinx.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2014-08-29target-arm: Make the ARM PMCCNTR register 64-bitAlistair Francis2-11/+10
This makes the PMCCNTR register 64-bit to allow for the 64-bit ARMv8 version. Signed-off-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com> Signed-off-by: Alistair Francis <alistair.francis@xilinx.com> Message-id: 6c5bac5fd0ea54963b1fc0e7f9464909f2e19a73.1409025949.git.peter.crosthwaite@xilinx.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2014-08-29hw/intc/arm_gic: honor target mask in gic_update()Sergey Fedorov1-1/+2
Take IRQ target mask into account when determining the highest priority pending interrupt. Signed-off-by: Sergey Fedorov <serge.fdrv@gmail.com> Acked-by: Christoffer Dall <christoffer.dall@linaro.org> Message-id: 1407947471-26981-1-git-send-email-serge.fdrv@gmail.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2014-08-29aarch64: raise max_cpus to 8Joel Schopp1-1/+1
I'm running on a system with 8 cpus and it would be nice to have qemu support all of them. The attached patch does that and has been tested. That said, I'm not sure if 8 is enough or if we want to bump this even higher now before systems with many more cpus come along. 255 anyone? Cc: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Joel Schopp <joel.schopp@amd.com> Message-id: 20140819213304.19537.2834.stgit@joelaarch64.amd.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2014-08-29arm_gic: Use GIC_NR_SGIS constantAdam Lackorzynski1-1/+1
Use constant rather than a plain number. Acked-by: Christoffer Dall <christoffer.dall@linaro.org> Signed-off-by: Adam Lackorzynski <adam@os.inf.tu-dresden.de> Message-id: 1408372255-12358-5-git-send-email-adam@os.inf.tu-dresden.de Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2014-08-29arm_gic: Do not force PPIs to edge-triggered modeAdam Lackorzynski1-1/+1
Only SGIs must be WI, done by forcing them to their default (edge-triggered). Acked-by: Christoffer Dall <christoffer.dall@linaro.org> Signed-off-by: Adam Lackorzynski <adam@os.inf.tu-dresden.de> Message-id: 1408372255-12358-4-git-send-email-adam@os.inf.tu-dresden.de Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2014-08-29arm_gic: GICD_ICFGR: Write model only for pre v1 GICsAdam Lackorzynski1-4/+6
Setting the model is only available in pre-v1 GIC models. Acked-by: Christoffer Dall <christoffer.dall@linaro.org> Signed-off-by: Adam Lackorzynski <adam@os.inf.tu-dresden.de> Message-id: 1408372255-12358-3-git-send-email-adam@os.inf.tu-dresden.de Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2014-08-29arm_gic: Fix read of GICD_ICFGRAdam Lackorzynski1-1/+1
The GICD_ICFGR register covers 4 interrupts per byte. Acked-by: Christoffer Dall <christoffer.dall@linaro.org> Signed-off-by: Adam Lackorzynski <adam@os.inf.tu-dresden.de> Message-id: 1408372255-12358-2-git-send-email-adam@os.inf.tu-dresden.de Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2014-08-29target-arm: Correct Cortex-A57 ISAR5 and AA64ISAR0 ID register valuesPeter Maydell1-1/+2
We implement the crypto extensions but were incorrectly reporting ID register values for the Cortex-A57 which did not advertise crypto. Use the correct values as described in the TRM. With this fix Linux correctly detects presence of the crypto features and advertises them in /proc/cpuinfo. Reported-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 1408718660-7295-1-git-send-email-peter.maydell@linaro.org Cc: qemu-stable@nongnu.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2014-08-29target-arm: Fix regression that disabled VFP for ARMv5 CPUsPeter Maydell1-1/+8
Commit 2c7ffc414 added support for honouring the CPACR coprocessor access control register bits which may disable access to VFP and Neon instructions. However it failed to account for the fact that the CPACR is only present starting from the ARMv6 architecture version, so it accidentally disabled VFP completely for ARMv5 CPUs like the ARM926. Linux would detect this as "no VFP present" and probably fall back to its own emulation, but other guest OSes might crash or misbehave. This fixes bug LP:1359930. Reported-by: Jakub Jermar <jakub@jermar.eu> Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 1408714940-7192-1-git-send-email-peter.maydell@linaro.org Cc: qemu-stable@nongnu.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2014-08-29disas/libvixl: Update to upstream VIXL 1.5Peter Maydell13-93/+558
Update our copy of libvixl to upstream's 1.5 release. This includes the upstream versions of the fixes we were carrying locally (commit ffebe899). Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 1407162987-4659-1-git-send-email-peter.maydell@linaro.org
2014-08-29Merge remote-tracking branch 'remotes/kraxel/tags/pull-usb-20140829-1' into ↵Peter Maydell14-14/+264
staging usb: bugfix collection. usb: add cleanup functions for host adapters, in preparation for hotplug support. usb: add simple qtests for uhci,ohci,xhci. # gpg: Signature made Fri 29 Aug 2014 12:56:20 BST using RSA key ID D3E87138 # gpg: Good signature from "Gerd Hoffmann (work) <kraxel@redhat.com>" # gpg: aka "Gerd Hoffmann <gerd@kraxel.org>" # gpg: aka "Gerd Hoffmann (private) <kraxel@gmail.com>" * remotes/kraxel/tags/pull-usb-20140829-1: tests: add xHCI qtest tests: add UHCI qtest tests: add OHCI qtest usb: add usb host adapters exit trace usb-xhci: add exit function usb-ehci: add ehci-pci device exit function usb-ehci: add ehci unrealize funciton usb-ehci: add vmstate properity for EHCIState usb-uhci: clean up uhci resource when pci-uhci exit usb-ohci: add exit function usb-ohci: Fix memory leak for ohci timer usb: add usb_bus_release function Revert "xhci: Fix number of streams allocated when using streams" xhci: use (1u << i) Fix OHCI ISO TD state never being written back. xhci: fix debug print compiling error usb: Fix bootindex for portnr > 9 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2014-08-29tests: add xHCI qtestGonglei2-0/+38
Signed-off-by: Gonglei <arei.gonglei@huawei.com> Signed-off-by: Gerd Hoffmann <kraxel@redhat.com>
2014-08-29tests: add UHCI qtestGonglei2-1/+38
Signed-off-by: Gonglei <arei.gonglei@huawei.com> Signed-off-by: Gerd Hoffmann <kraxel@redhat.com>
2014-08-29tests: add OHCI qtestGonglei3-1/+39
Signed-off-by: Gonglei <arei.gonglei@huawei.com> Signed-off-by: Gerd Hoffmann <kraxel@redhat.com>
2014-08-29usb: add usb host adapters exit traceGonglei4-0/+9
Signed-off-by: Gonglei <arei.gonglei@huawei.com> Signed-off-by: Gerd Hoffmann <kraxel@redhat.com>
2014-08-29usb-xhci: add exit functionGonglei1-0/+36
clean up xhci resource when xhci pci device exit. Signed-off-by: Gonglei <arei.gonglei@huawei.com> Signed-off-by: Gerd Hoffmann <kraxel@redhat.com>
2014-08-29usb-ehci: add ehci-pci device exit functionGonglei1-0/+14
clean up ehci resource when ehci pci device exit. Signed-off-by: Gonglei <arei.gonglei@huawei.com> Signed-off-by: Gerd Hoffmann <kraxel@redhat.com>
2014-08-29usb-ehci: add ehci unrealize funcitonGonglei2-0/+26
cleanup ehci controller resource, both pci and sysbus if they're necessary. Signed-off-by: Gonglei <arei.gonglei@huawei.com> Signed-off-by: Gerd Hoffmann <kraxel@redhat.com>
2014-08-29usb-ehci: add vmstate properity for EHCIStateGonglei2-1/+2
since hotunplug the ehci host adapter, we should delete vm_change_state_handler also, so the VMChangeStateEntry should be saved in EHCIState. Signed-off-by: Gonglei <arei.gonglei@huawei.com> Signed-off-by: Gerd Hoffmann <kraxel@redhat.com>
2014-08-29usb-uhci: clean up uhci resource when pci-uhci exitGonglei1-0/+22
clean up uhci resource when uhci pci device exit. Signed-off-by: Gonglei <arei.gonglei@huawei.com> Signed-off-by: Gerd Hoffmann <kraxel@redhat.com>
2014-08-29usb-ohci: add exit functionGonglei1-0/+19
clean up ohci resource when ohci pci device exit. Signed-off-by: Gonglei <arei.gonglei@huawei.com> Signed-off-by: Gerd Hoffmann <kraxel@redhat.com>
2014-08-29usb-ohci: Fix memory leak for ohci timerGonglei1-1/+3
Signed-off-by: Gonglei <arei.gonglei@huawei.com> Signed-off-by: Gerd Hoffmann <kraxel@redhat.com>
2014-08-29usb: add usb_bus_release functionGonglei2-0/+8
add global variables releasing logic when the usb buses were removed or hot-unpluged. Signed-off-by: Gonglei <arei.gonglei@huawei.com> Signed-off-by: Gerd Hoffmann <kraxel@redhat.com>
2014-08-29Revert "xhci: Fix number of streams allocated when using streams"Gerd Hoffmann1-1/+1
This reverts commit d063c3112c4cd23a479ee18720c2bd119da2d315. "2 << x" is the same as "2 ^ (x + 1)", so the old code is correct. Signed-off-by: Gerd Hoffmann <kraxel@redhat.com>
2014-08-29xhci: use (1u << i)Gerd Hoffmann1-2/+2
Signed-off-by: Gerd Hoffmann <kraxel@redhat.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
2014-08-29Fix OHCI ISO TD state never being written back.Jack Un1-2/+2
There appears to be typo in OHCI with isochronous transfers resulting in isoch. transfer descriptor state never being written back. The'put_words' function is in a OR statement hence it is never called. Signed-off-by: Jack Un <jack.un@gmail.com> Signed-off-by: Gerd Hoffmann <kraxel@redhat.com>
2014-08-29xhci: fix debug print compiling errorGonglei1-3/+3
after commit 003e15a180373048f0c1f4df0bfe303746eb2676 the DPRINTF will broke compiling, adjust its location. Signed-off-by: Gonglei <arei.gonglei@huawei.com> Signed-off-by: Gerd Hoffmann <kraxel@redhat.com>
2014-08-29usb: Fix bootindex for portnr > 9Markus Armbruster1-2/+2
We identify devices by their Open Firmware device paths. The encoding of the host controller and hub port numbers is incorrect: usb_get_fw_dev_path() formats them in decimal, while SeaBIOS uses hexadecimal. When some port number > 9, SeaBIOS will miss the bootindex (lucky case), or apply it to another device (unlucky case). The relevant spec[*] agrees with SeaBIOS (and OVMF, for that matter). Change %d to %x. Bug can bite only with host controllers or hubs sporting more than ten ports. I'm not aware of any. [*] Open Firmware Recommended Practice: Universal Serial Bus, Version 1, Section 3.2.1 Device Node Address Representation http://www.openfirmware.org/1275/bindings/usb/usb-1_0.ps Signed-off-by: Markus Armbruster <armbru@redhat.com> Reviewed-by: Laszlo Ersek <lersek@redhat.com> Note: xhci can be configured with up to 15 ports (default is 4 ports). Signed-off-by: Gerd Hoffmann <kraxel@redhat.com>
2014-08-28Merge remote-tracking branch 'remotes/bonzini/tags/for-upstream' into stagingPeter Maydell13-122/+141
SCSI patches include bug fixes from Fam and Peter, improved error reporting from Fam and a fix for DPRINTF bitrot. Memory patches try again to initialize name from the QOM name. # gpg: Signature made Thu 28 Aug 2014 15:10:31 BST using RSA key ID 9B4D86F2 # gpg: Good signature from "Paolo Bonzini <pbonzini@redhat.com>" # gpg: aka "Paolo Bonzini <bonzini@gnu.org>" * remotes/bonzini/tags/for-upstream: memory: Lazy init name from QOM name as needed xen: hvm: Abstract away memory region name ref xen-hvm: Constify string virtio-scsi: Report error if num_queues is 0 or too large scsi-generic: remove superfluous DPRINTF avoid to break compiling block/iscsi: fix memory corruption on iscsi resize scsi-bus: Convert DeviceClass init to realize block: Pass errp in blkconf_geometry Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2014-08-28Merge remote-tracking branch 'remotes/kvm/tags/for-upstream' into stagingPeter Maydell22-73/+394
Mostly bugfixes + Alexey's interface-based implementation of the NMI monitor command. # gpg: Signature made Thu 28 Aug 2014 15:07:22 BST using RSA key ID 9B4D86F2 # gpg: Good signature from "Paolo Bonzini <pbonzini@redhat.com>" # gpg: aka "Paolo Bonzini <bonzini@gnu.org>" * remotes/kvm/tags/for-upstream: mc146818rtc: reinitialize irq_reinject_on_ack_count on reset target-i386: Add "tsc_adjust" CPU feature name target-i386: Add "mpx" CPU feature name vl: process -object after other backend options checkpatch.pl: adjust typedef definition to QEMU coding style x86: Clear MTRRs on vCPU reset x86: kvm: Add MTRR support for kvm_get|put_msrs() x86: Use common variable range MTRR counts target-i386: Don't forbid NX bit on PAE PDEs and PTEs spapr: Add support for new NMI interface s390x: Migrate to new NMI interface s390x: Convert QEMUMachine to MachineClass cpus: Define callback for QEMU "nmi" command kvm: run cpu state synchronization on target vcpu thread Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2014-08-28memory: Lazy init name from QOM name as neededPeter Crosthwaite1-0/+4
To support name retrieval of MemoryRegions that were created dynamically (that is, not via memory_region_init and friends). We cache the name in MemoryRegion's state as object_get_canonical_path_component mallocs the returned value so it's not suitable for direct return to callers. Memory already frees the name field, so this will be garbage collected along with the MR object. Signed-off-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2014-08-28xen: hvm: Abstract away memory region name refPeter Crosthwaite1-3/+6
The mr->name field is removed. This slipped through compile testing. Fix. Reviewed-by: Stefan Weil <sw@weilnetz.de> Signed-off-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2014-08-28xen-hvm: Constify stringPeter Crosthwaite1-2/+2
It's constant, and sourced from existing const strings. Avoid dodgy casts by converting to const. Signed-off-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com> Reviewed-by: Stefan Weil <sw@weilnetz.de> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2014-08-28Merge remote-tracking branch ↵Peter Maydell6-31/+24
'remotes/stefanha/tags/fix-buildbot-12082014-pull-request' into staging Pull request # gpg: Signature made Thu 28 Aug 2014 13:43:00 BST using RSA key ID 81AB73C8 # gpg: Good signature from "Stefan Hajnoczi <stefanha@redhat.com>" # gpg: aka "Stefan Hajnoczi <stefanha@gmail.com>" * remotes/stefanha/tags/fix-buildbot-12082014-pull-request: Revert "qemu-img: sort block formats in help message" block: sort formats alphabetically in bdrv_iterate_format() mirror: fix uninitialized variable delay_ns warnings trace: avoid Python 2.5 all() in tracetool libqtest: launch QEMU with QEMU_AUDIO_DRV=none qapi.py: avoid Python 2.5+ any() function Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2014-08-28Revert "qemu-img: sort block formats in help message"Stefan Hajnoczi1-22/+3
This reverts commit 1a443c1b8b4314d365e82bddeb1de5b4b1c15fb3 and the later commit 395071a76328189f50c778f4dee6dabb90503dd9. GSequence was introduced in glib 2.14. RHEL 5 fails to compile since it uses glib 2.12.3. Now that bdrv_iterate_format() invokes the iteration callback in sorted order these commits are unnecessary. Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com> Reviewed-by: Benoît Canet <benoit.canet@nodalink.com>
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