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2015-09-09add macro file for coccinellePaolo Bonzini1-0/+119
Coccinelle chokes on some idioms from compiler.h and queue.h. Extract those in a macro file, to be used with "--macro-file scripts/cocci-macro-file.h". Reviewed-by: Markus Armbruster <armbru@redhat.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2015-09-09configure: factor out adding disas configurePeter Crosthwaite1-40/+25
Every arch adds its disas configury to both its own config as well config_disas_all. Make a small function do to both at once. Signed-off-by: Peter Crosthwaite <crosthwaite.peter@gmail.com> Message-Id: <1440844439-19391-1-git-send-email-crosthwaite.peter@gmail.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2015-09-09vhost-scsi: fix wrong vhost-scsi firmware pathGonglei1-1/+1
vhost-scsi bootindex does't work because Qemu passes wrong fireware path to seabios. before: /pci@i0cf8/scsi@7channel@0/vhost-scsi@0,0 after applying the patch: /pci@i0cf8/scsi@7/channel@0/vhost-scsi@0,0 Reported-by: Subo <subo7@huawei.com> Signed-off-by: Gonglei <arei.gonglei@huawei.com> Message-Id: <1440553971-11108-1-git-send-email-arei.gonglei@huawei.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2015-09-09checkpatch: remove tests that are not relevant outside the kernelPaolo Bonzini1-389/+12
Fully removing Sparse support requires more invasive changes. Only remove the really kernel-specific parts such as address space names. Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2015-09-09checkpatch: adapt some tests to QEMUPaolo Bonzini1-81/+60
Mostly change severity levels, but some tests can also be adjusted to refer to QEMU APIs or data structures. Reviewed-by: Stefan Hajnoczi <stefanha@redhat.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2015-09-09CODING_STYLE: update mixed declaration rulesPaolo Bonzini1-4/+9
Mixed declarations do come in handy at the top of #ifdef blocks. Reluctantly allow this particular usage and suggest an alternative. Reviewed-by: Stefan Hajnoczi <stefanha@redhat.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2015-09-09qmp: Add example usage of strto*l() qemu wrapperCarlos L. Torres1-4/+10
Signed-off-by: Carlos L. Torres <carlos.torres@rackspace.com> Message-Id: <11ac63e95d88551f1c2c9b1216b15d3cb8ba4468.1437346779.git.carlos.torres@rackspace.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2015-09-09cutils: Add qemu_strtoull() wrapperCarlos L. Torres3-0/+348
Add wrapper for strtoull() function. Include unit tests. Signed-off-by: Carlos L. Torres <carlos.torres@rackspace.com> Message-Id: <e0f0f611c9a81f3c29f451d0b17d755dfab1e90a.1437346779.git.carlos.torres@rackspace.com> [Use uint64_t in prototype. - Paolo] Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2015-09-09cutils: Add qemu_strtoll() wrapperCarlos L. Torres3-0/+345
Add wrapper for strtoll() function. Include unit tests. Signed-off-by: Carlos L. Torres <carlos.torres@rackspace.com> Message-Id: <7454a6bb9ec03b629e8beb4f109dd30dc2c9804c.1437346779.git.carlos.torres@rackspace.com> [Use int64_t in prototype, since that's what QEMU uses. - Paolo] Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2015-09-09cutils: Add qemu_strtoul() wrapperCarlos L. Torres3-0/+352
Add wrapper for strtoul() function. Include unit tests. Signed-off-by: Carlos L. Torres <carlos.torres@rackspace.com> Message-Id: <9621b4ae8e35fded31c715c2ae2a98f904f07ad0.1437346779.git.carlos.torres@rackspace.com> [Fix tests for 32-bit build. - Paolo] Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2015-09-09cutils: Add qemu_strtol() wrapperCarlos L. Torres3-0/+379
Add wrapper for strtol() function. Include unit tests. Signed-off-by: Carlos L. Torres <carlos.torres@rackspace.com> Message-Id: <07199f1c0ff3892790c6322123aee1e92f580550.1437346779.git.carlos.torres@rackspace.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2015-09-09translate-all: remove obsolete comment about l1_mapEmilio G. Cota1-2/+1
l1_map is based on physical addresses in full-system mode, as pointed out in an earlier comment. Said comment also mentions that virtual addresses are only used in l1_map in user-only mode. Signed-off-by: Emilio G. Cota <cota@braap.org> Message-Id: <1440375847-17603-11-git-send-email-cota@braap.org> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2015-09-09linux-user: call rcu_(un)register_thread on pthread_(exit|create)Emilio G. Cota1-0/+2
Signed-off-by: Emilio G. Cota <cota@braap.org> Message-Id: <1440375847-17603-13-git-send-email-cota@braap.org> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2015-09-09rcu: fix comment with s/rcu_gp_lock/rcu_registry_lock/Emilio G. Cota1-1/+1
Signed-off-by: Emilio G. Cota <cota@braap.org> Message-Id: <1440375847-17603-10-git-send-email-cota@braap.org> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2015-09-09rcu: init rcu_registry_lock after forkEmilio G. Cota1-1/+6
We were unlocking this lock after fork, which is wrong since only the thread that holds a mutex is allowed to unlock it. Signed-off-by: Emilio G. Cota <cota@braap.org> Message-Id: <1440375847-17603-9-git-send-email-cota@braap.org> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2015-09-09Makefile.target: include top level build dir in vpathMichael Marineau1-1/+1
Using ccache with CCACHE_BASEDIR set to $(SRC_PATH) or a parent will rewrite all absolute paths to relative paths. This interacts poorly with QEMU's two-level build directory scheme. For example, lets say BUILD_DIR=$(SRC_PATH)/build so build/blockdev.d will contain: blockdev.o: ../blockdev.c ../include/sysemu/block-backend.h \ Now the target build under build/x86_64-softmmu or similar will depend on ../blockdev.o which in turn will get make to source ../blockdev.d to check its dependencies. Since make always considers paths relative to the current working directory rather than the makefile the path appeared in the relative path to ../blockdev.c is useless. This change simply adds the top level build directory to vpath so paths relative to the source directory, top build directory, and target build directory all work just fine. Signed-off-by: Michael Marineau <michael.marineau@coreos.com> Message-Id: <1439103775-11836-1-git-send-email-michael.marineau@coreos.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2015-09-09Move RAMBlock and ram_list to ram_addr.hDr. David Alan Gilbert2-41/+40
Signed-off-by: Dr. David Alan Gilbert <dgilbert@redhat.com> Message-Id: <1439547914-18249-1-git-send-email-dgilbert@redhat.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2015-09-09tcg: signal-free qemu_cpu_kickPaolo Bonzini4-72/+27
Signals are slow and do not exist on Win32. The previous patches have done most of the legwork to introduce memory barriers (some of them were even there already for the sake of Windows!) and we can now set the flags directly in the iothread. qemu_cpu_kick_thread is not used anymore on TCG, since the TCG thread is never outside usermode while the CPU is running (not halted). Instead run the content of the signal handler (now in qemu_cpu_kick_no_halt) directly. qemu_cpu_kick_no_halt is also used in qemu_mutex_lock_iothread to avoid the overhead of qemu_cond_broadcast. Reviewed-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2015-09-09use qemu_cpu_kick instead of cpu_exit or qemu_cpu_kick_threadPaolo Bonzini3-11/+10
Use the same API to trigger interruption of a CPU, no matter if under TCG or KVM. There is no difference: these calls come from the CPU thread, so the qemu_cpu_kick calls will send a signal to the running thread and it will be processed synchronously, just like a call to cpu_exit. The only difference is in the overhead, but neither call to cpu_exit (now qemu_cpu_kick) is in a hot path. Reviewed-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2015-09-09tcg: synchronize exit_request and tcg_current_cpu accessesPaolo Bonzini2-5/+11
Synchronize the remaining pair of accesses in cpu_signal. These should be necessary on Windows as well, at least in theory. Probably SuspendProcess and ResumeProcess introduce some implicit memory barrier. Reviewed-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2015-09-09tcg: synchronize cpu->exit_request and cpu->tcg_exit_req accessesPaolo Bonzini2-1/+7
Reviewed-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2015-09-09tcg: assign cpu->current_tb in a simpler placePaolo Bonzini1-8/+2
TCG has not been reading cpu->current_tb from signal handlers for years. The code that synchronized cpu_exec with the signal handler is not needed anymore. Reviewed-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2015-09-09remove qemu/tls.hPaolo Bonzini3-56/+2
TLS is now required on all platforms, so DECLARE_TLS/DEFINE_TLS is not needed anymore. Removing it does not break Windows because of the previous patch. Reviewed-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2015-09-09tcg: introduce tcg_current_cpuPaolo Bonzini3-11/+9
This is already useful on Windows in order to remove tls.h, because accesses to current_cpu are done from a different thread on that platform. It will be used on POSIX platforms as soon TCG stops using signals to interrupt the execution of translated code. Reviewed-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2015-09-09i8257: remove cpu_request_exit irqPaolo Bonzini11-77/+13
This is unused. cpu_exit now is almost exclusively an internal function to the CPU execution loop. In a few patches, we'll change the remaining occurrences to qemu_cpu_kick, making it truly internal. Reviewed-by: Richard henderson <rth@twiddle.net> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2015-09-09i8257: rewrite DMA_schedule to avoid hooking into the CPU loopPaolo Bonzini5-10/+16
The i8257 DMA controller uses an idle bottom half, which by default does not cause the main loop to exit. Therefore, the DMA_schedule function is there to ensure that the CPU relinquishes the iothread mutex to the iothread. However, this is not enough since the iothread will call aio_compute_timeout() and go to sleep again. In the iothread world, forcing execution of the idle bottom half is much simpler, and only requires a call to qemu_notify_event(). Do it, removing the need for the "cpu_request_exit" pseudo-irq. The next patch will remove it. Reviewed-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2015-09-07Added generic panic handler qemu_system_guest_panicked()Andrey Smetanin4-11/+10
There are pieces of guest panic handling code that can be shared in one generic function. These code replaced by call qemu_system_guest_panicked(). Signed-off-by: Andrey Smetanin <asmetanin@virtuozzo.com> Signed-off-by: Denis V. Lunev <den@openvz.org> CC: Paolo Bonzini <pbonzini@redhat.com> CC: Andreas Färber <afaerber@suse.de> Message-Id: <1435924905-8926-10-git-send-email-den@openvz.org> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2015-09-07block/iscsi: validate block size returned from targetPeter Lieven1-0/+4
It has been reported that at least tgtd returns a block size of 0 for LUN 0. To avoid running into divide by zero later on and protect against other problematic block sizes validate the block size right at connection time. Cc: qemu-stable@nongnu.org Reported-by: Andrey Korolyov <andrey@xdel.ru> Signed-off-by: Peter Lieven <pl@kamp.de> Message-Id: <1439552016-8557-1-git-send-email-pl@kamp.de> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2015-09-07iohandler: Use aio APIFam Zheng3-100/+19
iohandler.c shares the same interface with aio, but with duplicated code. It's better to rebase iohandler, also because that aio is a more friendly interface to multi-threads. Create a global AioContext instance and let its GSource handle the iohandler events. Signed-off-by: Fam Zheng <famz@redhat.com> Message-Id: <1441596538-4412-1-git-send-email-famz@redhat.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2015-09-07cpus.c: qemu_mutex_lock_iothread fix race condition at cpu thread initAníbal Limón1-1/+1
When QEMU starts the RCU thread executes qemu_mutex_lock_thread causing error "qemu:qemu_cpu_kick_thread: No such process" and exits. This isn't occur frequently but in glibc the thread id can exist and this not guarantee that the thread is on active/running state. If is inserted a sleep(1) after newthread assignment [1] the issue appears. So not make assumption that thread exist if first_cpu->thread is set then change the validation of cpu to created that is set into cpu threads (kvm, tcg, dummy). [1] https://sourceware.org/git/?p=glibc.git;a=blob;f=nptl/pthread_create.c;h=d10f4ea8004e1d8f3a268b95cc0f8d93b8d89867;hb=HEAD#l621 Cc: qemu-stable@nongnu.org Signed-off-by: Aníbal Limón <anibal.limon@linux.intel.com> Message-Id: <1441313313-3040-1-git-send-email-anibal.limon@linux.intel.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2015-09-07seqlock: read sequence number atomicallyEmilio G. Cota1-3/+3
With this change we make sure that the compiler will not optimise the read of the sequence number in any way. Signed-off-by: Emilio G. Cota <cota@braap.org> Message-Id: <1440375847-17603-8-git-send-email-cota@braap.org> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2015-09-07seqlock: add missing 'inline' to seqlock_read_retryEmilio G. Cota1-1/+1
Signed-off-by: Emilio G. Cota <cota@braap.org> Message-Id: <1440375847-17603-7-git-send-email-cota@braap.org> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2015-09-02qemu-thread: handle spurious futex_wait wakeupsEmilio G. Cota1-1/+10
Signed-off-by: Emilio G. Cota <cota@braap.org> Message-Id: <1440375847-17603-12-git-send-email-cota@braap.org> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2015-08-28s390: fix softmmu compilationLaurent Vivier1-2/+2
guest_base must be used only in linux-user mode. Signed-off-by: Laurent Vivier <laurent@vivier.eu> Message-id: 1440757421-9674-1-git-send-email-laurent@vivier.eu Reviewed-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2015-08-28qemu-doc.texi: Fix capitalization error in OS X build instructionsPeter Maydell1-1/+1
Fix a capitalization error in the OS X build instructions; this was picked up in review of commit b352153f5f and intended to be corrected before I applied it, but I accidentally didn't include it. Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2015-08-27From: John Arbuckle <programmingkidx@gmail.com>G 31-3/+57
qemu-doc.texi: Add information on compiling source code on Mac OS X Add information to the documentation on how to build QEMU on Mac OS X. Signed-off-by: John Arbuckle <programmingkidx@gmail.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> [PMM: fixed a minor capitalization error] Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2015-08-27Merge remote-tracking branch 'remotes/weil/tags/pull-tci-20150826' into stagingPeter Maydell1-5/+1
tci patch queue # gpg: Signature made Wed 26 Aug 2015 19:51:07 BST using RSA key ID 677450AD # gpg: Good signature from "Stefan Weil <sw@weilnetz.de>" # gpg: aka "Stefan Weil <stefan.weil@weilnetz.de>" # gpg: aka "Stefan Weil <stefan.weil@bib.uni-mannheim.de>" # gpg: WARNING: This key is not certified with a trusted signature! # gpg: There is no indication that the signature belongs to the owner. # Primary key fingerprint: 4923 6FEA 75C9 5D69 8EC2 B78A E08C 21D5 6774 50AD * remotes/weil/tags/pull-tci-20150826: exec-all: Translate TCI return addresses backwards too Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2015-08-26exec-all: Translate TCI return addresses backwards tooPeter Crosthwaite1-5/+1
This subtraction of return addresses applies directly to TCI as well as host-TCG. This fixes Linux boots for at least Microblaze, CRIS, ARM and SH4 when using TCI. [sw: Removed indentation for preprocessor statement] [sw: The patch also fixes Linux boot for x86_64] Reviewed-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Stefan Weil <sw@weilnetz.de> Signed-off-by: Peter Crosthwaite <crosthwaite.peter@gmail.com>
2015-08-26Merge remote-tracking branch ↵Peter Maydell1-5/+10
'remotes/kraxel/tags/pull-cve-2015-5225-20150826-1' into staging vnc: fix memory corruption (CVE-2015-5225) # gpg: Signature made Wed 26 Aug 2015 17:37:21 BST using RSA key ID D3E87138 # gpg: Good signature from "Gerd Hoffmann (work) <kraxel@redhat.com>" # gpg: aka "Gerd Hoffmann <gerd@kraxel.org>" # gpg: aka "Gerd Hoffmann (private) <kraxel@gmail.com>" * remotes/kraxel/tags/pull-cve-2015-5225-20150826-1: vnc: fix memory corruption (CVE-2015-5225) Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2015-08-26vnc: fix memory corruption (CVE-2015-5225)Gerd Hoffmann1-5/+10
The _cmp_bytes variable added by commit "bea60dd ui/vnc: fix potential memory corruption issues" can become negative. Result is (possibly exploitable) memory corruption. Reason for that is it uses the stride instead of bytes per scanline to apply limits. For the server surface is is actually fine. vnc creates that itself, there is never any padding and thus scanline length always equals stride. For the guest surface scanline length and stride are typically identical too, but it doesn't has to be that way. So add and use a new variable (guest_ll) for the guest scanline length. Also rename min_stride to line_bytes to make more clear what it actually is. Finally sprinkle in an assert() to make sure we never use a negative _cmp_bytes again. Reported-by: 范祚至(库特) <zuozhi.fzz@alibaba-inc.com> Reviewed-by: P J P <ppandit@redhat.com> Signed-off-by: Gerd Hoffmann <kraxel@redhat.com>
2015-08-25Merge remote-tracking branch ↵Peter Maydell8-63/+629
'remotes/pmaydell/tags/pull-target-arm-20150825-1' into staging target-arm queue: * add missing EL2/EL3 TLBI operations * add missing EL2/EL3 ATS operations * add missing EL2/EL3 registers * update Xilinx MAINTAINERS info * Xilinx: connect the four OCM banks # gpg: Signature made Tue 25 Aug 2015 16:22:43 BST using RSA key ID 14360CDE # gpg: Good signature from "Peter Maydell <peter.maydell@linaro.org>" # gpg: aka "Peter Maydell <pmaydell@gmail.com>" # gpg: aka "Peter Maydell <pmaydell@chiark.greenend.org.uk>" * remotes/pmaydell/tags/pull-target-arm-20150825-1: target-arm: Implement AArch64 TLBI operations on IPAs target-arm: Implement missing EL3 TLB invalidate operations target-arm: Implement missing EL2 TLBI operations target-arm: Restrict AArch64 TLB flushes to the MMU indexes they must touch target-arm: Move TLBI ALLE1/ALLE1IS definitions into numeric order cputlb: Add functions for flushing TLB for a single MMU index target-arm: Implement AArch32 ATS1H* operations target-arm: Enable the AArch32 ATS12NSO ops target-arm: Add CP_ACCESS_TRAP_UNCATEGORIZED_EL2, 3 target-arm: Wire up AArch64 EL2 and EL3 address translation ops target-arm: there is no TTBR1 for 32-bit EL2 stage 1 translations target-arm: Implement missing ACTLR registers target-arm: Implement missing AFSR registers target-arm: Implement missing AMAIR registers target-arm: Add missing MAIR_EL3 and TPIDR_EL3 registers MAINTAINERS: Add ZynqMP to MAINTAINERS file MAINTAINERS: Update Xilinx Maintainership xlnx-zynqmp: Connect the four OCM banks Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2015-08-25target-arm: Implement AArch64 TLBI operations on IPAsPeter Maydell1-0/+55
Implement the AArch64 TLBI operations which take an intermediate physical address and invalidate stage 2 translations. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Message-id: 1439548879-1972-7-git-send-email-peter.maydell@linaro.org
2015-08-25target-arm: Implement missing EL3 TLB invalidate operationsPeter Maydell1-0/+76
Implement the remaining stage 1 TLB invalidate operations visible from EL3. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Message-id: 1439548879-1972-6-git-send-email-peter.maydell@linaro.org
2015-08-25target-arm: Implement missing EL2 TLBI operationsPeter Maydell1-0/+22
Implement the missing TLBI operations that exist only if EL2 is implemented. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Message-id: 1439548879-1972-5-git-send-email-peter.maydell@linaro.org
2015-08-25target-arm: Restrict AArch64 TLB flushes to the MMU indexes they must touchPeter Maydell1-43/+129
Now we have the ability to flush the TLB only for specific MMU indexes, update the AArch64 TLB maintenance instruction implementations to only flush the parts of the TLB they need to, rather than doing full flushes. We take the opportunity to remove some duplicate functions (the per-asid tlb ops work like the non-per-asid ones because we don't support flushing a TLB only by ASID) and to bring the function names in line with the architectural TLBI operation names. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Message-id: 1439548879-1972-4-git-send-email-peter.maydell@linaro.org
2015-08-25target-arm: Move TLBI ALLE1/ALLE1IS definitions into numeric orderPeter Maydell1-8/+8
Move the two regdefs for TLBI ALLE1 and TLBI ALLE1IS down so that the whole set of AArch64 TLBI regdefs is arranged in numeric order. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Message-id: 1439548879-1972-3-git-send-email-peter.maydell@linaro.org
2015-08-25cputlb: Add functions for flushing TLB for a single MMU indexPeter Maydell2-0/+144
Guest CPU TLB maintenance operations may be sufficiently specialized to only need to flush TLB entries corresponding to a particular MMU index. Implement cputlb functions for this, to avoid the inefficiency of flushing TLB entries which we don't need to. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Message-id: 1439548879-1972-2-git-send-email-peter.maydell@linaro.org
2015-08-25target-arm: Implement AArch32 ATS1H* operationsPeter Maydell1-0/+22
Implement the AArch32 ATS1H* operations which perform Hyp mode stage 1 translations. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Message-id: 1437751263-21913-6-git-send-email-peter.maydell@linaro.org
2015-08-25target-arm: Enable the AArch32 ATS12NSO opsPeter Maydell1-5/+11
Apply the correct conditions in the ats_access() function for the ATS12NSO* address translation operations: * succeed at EL2 or EL3 * normal UNDEF trap from NS EL1 * trap to EL3 from S EL1 (only possible if EL3 is AArch64) (This change means they're now available in our EL3-supporting CPUs when they would previously always UNDEF.) Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Message-id: 1437751263-21913-5-git-send-email-peter.maydell@linaro.org
2015-08-25target-arm: Add CP_ACCESS_TRAP_UNCATEGORIZED_EL2, 3Peter Maydell2-0/+11
Some coprocessor register access functions need to be able to report "trap to EL3 with an 'uncategorized' syndrome"; add the necessary CPAccessResult enum and handling for it. I don't currently know of any registers that need to trap to EL2 with the 'uncategorized' syndrome, but adding the _EL2 enum as well is trivial and fills in what would otherwise be an odd gap in the handling. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Message-id: 1437751263-21913-4-git-send-email-peter.maydell@linaro.org
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