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2015-10-08Merge remote-tracking branch 'remotes/rth/tags/pull-tcg-20151007' into stagingPeter Maydell45-1492/+964
Do away with TB retranslation # gpg: Signature made Wed 07 Oct 2015 10:42:08 BST using RSA key ID 4DD0279B # gpg: Good signature from "Richard Henderson <rth7680@gmail.com>" # gpg: aka "Richard Henderson <rth@redhat.com>" # gpg: aka "Richard Henderson <rth@twiddle.net>" * remotes/rth/tags/pull-tcg-20151007: (26 commits) tcg: Adjust CODE_GEN_AVG_BLOCK_SIZE tcg: Check for overflow via highwater mark tcg: Allocate a guard page after code_gen_buffer tcg: Emit prologue to the beginning of code_gen_buffer tcg: Remove tcg_gen_code_search_pc tcg: Remove gen_intermediate_code_pc tcg: Save insn data and use it in cpu_restore_state_from_tb tcg: Pass data argument to restore_state_to_opc tcg: Add TCG_MAX_INSNS target-*: Drop cpu_gen_code define tcg: Merge cpu_gen_code into tb_gen_code target-sparc: Add npc state to insn_start target-sparc: Remove gen_opc_jump_pc target-sparc: Split out gen_branch_n target-sparc: Tidy gen_branch_a interface target-cris: Mirror gen_opc_pc into insn_start target-sh4: Add flags state to insn_start target-s390x: Add cc_op state to insn_start target-mips: Add delayed branch state to insn_start target-i386: Add cc_op state to insn_start ... Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2015-10-08Merge remote-tracking branch 'remotes/rth/tags/pull-tile-20151007' into stagingPeter Maydell10-81/+799
Collected patches # gpg: Signature made Wed 07 Oct 2015 10:30:17 BST using RSA key ID 4DD0279B # gpg: Good signature from "Richard Henderson <rth7680@gmail.com>" # gpg: aka "Richard Henderson <rth@redhat.com>" # gpg: aka "Richard Henderson <rth@twiddle.net>" * remotes/rth/tags/pull-tile-20151007: target-tilegx: Support iret instruction and related special registers target-tilegx: Use TILEGX_EXCP_OPCODE_UNKNOWN and TILEGX_EXCP_OPCODE_UNIMPLEMENTED correctly target-tilegx: Implement v2mults instruction target-tilegx: Implement v?int_* instructions. target-tilegx: Implement v2sh* instructions target-tilegx: Handle nofault prefetch instructions target-tilegx: Fix a typo for mnemonic about "ld_add" target-tilegx: Use TILEGX_EXCP_SIGNAL instead of TILEGX_EXCP_SEGV target-tilegx: Decode ill pseudo-instructions linux-user/tilegx: Implement tilegx signal features linux-user/syscall_defs.h: Sync the latest si_code from Linux kernel target-tilegx: Let x1 pipe process bpt instruction only target-tilegx: Implement complex multiply instructions target-tilegx: Implement table index instructions target-tilegx: Implement crc instructions target-tilegx: Implement v1multu instruction target-tilegx: Implement v*add and v*sub instructions target-tilegx: Implement v*shl, v*shru, and v*shrs instructions target-tilegx: Tidy simd_helper.c Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2015-10-08Merge remote-tracking branch 'remotes/ehabkost/tags/numa-pull-request' into ↵Peter Maydell1-2/+3
staging NUMA queue, 2015-10-06 # gpg: Signature made Tue 06 Oct 2015 20:53:42 BST using RSA key ID 984DC5A6 # gpg: Good signature from "Eduardo Habkost <ehabkost@redhat.com>" * remotes/ehabkost/tags/numa-pull-request: pc-dimm: Fail realization for invalid nodes in non-NUMA config Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2015-10-07tcg: Adjust CODE_GEN_AVG_BLOCK_SIZERichard Henderson1-5/+6
At present, the "average" guestimate of TB size is way too small, leading to many unused entries in the pre-allocated TB array. For a guest with 1GB ram, we're currently allocating 256MB for the array. Survey arm, alpha, aarch64, ppc, sparc, i686, x86_64 guests running on x86_64 and ppc64 hosts and select a new average. The size of the array drops to 81MB with no more flushing than before. Reviewed-by: Aurelien Jarno <aurelien@aurel32.net> Signed-off-by: Richard Henderson <rth@twiddle.net>
2015-10-07tcg: Check for overflow via highwater markRichard Henderson4-16/+40
We currently pre-compute an worst case code size for any TB, which works out to be 122kB. Since the average TB size is near 1kB, this wastes quite a lot of storage. Instead, check for overflow in between generating code for each opcode. The overhead of the check isn't measurable and wastage is minimized. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <rth@twiddle.net>
2015-10-07tcg: Allocate a guard page after code_gen_bufferRichard Henderson1-91/+119
This will catch any overflow of the buffer. Add a native win32 alternative for alloc_code_gen_buffer; remove the malloc alternative. Signed-off-by: Richard Henderson <rth@twiddle.net>
2015-10-07tcg: Emit prologue to the beginning of code_gen_bufferRichard Henderson2-26/+37
By putting the prologue at the end, we risk overwriting the prologue should our estimate of maximum TB size. Given the two different placements of the call to tcg_prologue_init, move the high water mark computation into tcg_prologue_init. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <rth@twiddle.net>
2015-10-07tcg: Remove tcg_gen_code_search_pcRichard Henderson2-42/+19
It's no longer used, so tidy up everything reached by it. Reviewed-by: Aurelien Jarno <aurelien@aurel32.net> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <rth@twiddle.net>
2015-10-07tcg: Remove gen_intermediate_code_pcRichard Henderson22-736/+90
It is no longer used, so tidy up everything reached by it. This includes the gen_opc_* arrays, the search_pc parameter and the inline gen_intermediate_code_internal functions. Reviewed-by: Aurelien Jarno <aurelien@aurel32.net> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <rth@twiddle.net>
2015-10-07tcg: Save insn data and use it in cpu_restore_state_from_tbRichard Henderson4-55/+140
We can now restore state without retranslation. Reviewed-by: Aurelien Jarno <aurelien@aurel32.net> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <rth@twiddle.net>
2015-10-07tcg: Pass data argument to restore_state_to_opcRichard Henderson22-66/+79
The gen_opc_* arrays are already redundant with the data stored in the insn_start arguments. Transition restore_state_to_opc to use data from the latter. Reviewed-by: Aurelien Jarno <aurelien@aurel32.net> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <rth@twiddle.net>
2015-10-07tcg: Add TCG_MAX_INSNSRichard Henderson20-17/+95
Adjust all translators to respect it. Reviewed-by: Aurelien Jarno <aurelien@aurel32.net> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <rth@twiddle.net>
2015-10-07target-*: Drop cpu_gen_code defineRichard Henderson16-16/+0
This symbol no longer exists. Reviewed-by: Aurelien Jarno <aurelien@aurel32.net> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <rth@twiddle.net>
2015-10-07tcg: Merge cpu_gen_code into tb_gen_codeRichard Henderson2-74/+59
As it's only caller, this tidies things a bit. Reviewed-by: Aurelien Jarno <aurelien@aurel32.net> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <rth@twiddle.net>
2015-10-07target-sparc: Add npc state to insn_startRichard Henderson2-1/+7
Reviewed-by: Aurelien Jarno <aurelien@aurel32.net> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <rth@twiddle.net>
2015-10-07target-sparc: Remove gen_opc_jump_pcRichard Henderson1-9/+10
Since jump_pc[1] is always npc + 4, we can infer after incrementing that jump_pc[1] == pc + 4. Because of that, we can encode the branch destination into a single word, and store that in npc. Reviewed-by: Aurelien Jarno <aurelien@aurel32.net> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <rth@twiddle.net>
2015-10-07target-sparc: Split out gen_branch_nRichard Henderson1-27/+28
Unify three copies of this code from different branch types. Fix the case when npc == DYNAMIC_PC, i.e. a branch within a delay slot. Reviewed-by: Aurelien Jarno <aurelien@aurel32.net> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <rth@twiddle.net>
2015-10-07target-sparc: Tidy gen_branch_a interfaceRichard Henderson1-11/+10
We always pass pc2 == dc->npc and r_cond == cpu_cond, and always set is_br afterward. Infer all of that. Reviewed-by: Aurelien Jarno <aurelien@aurel32.net> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <rth@twiddle.net>
2015-10-07target-cris: Mirror gen_opc_pc into insn_startRichard Henderson1-1/+2
This perhaps isn't ideal in terms of (ab)using the "pc" field to encode both pc and ppc + delay branch state, as one has to be aware of this when examining opcode dumps. But it preserves existing logic, which will be good for bisection, and it certainly does save storage space. Reviewed-by: Aurelien Jarno <aurelien@aurel32.net> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <rth@twiddle.net>
2015-10-07target-sh4: Add flags state to insn_startRichard Henderson2-1/+2
Reviewed-by: Aurelien Jarno <aurelien@aurel32.net> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <rth@twiddle.net>
2015-10-07target-s390x: Add cc_op state to insn_startRichard Henderson2-1/+2
Reviewed-by: Aurelien Jarno <aurelien@aurel32.net> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <rth@twiddle.net>
2015-10-07target-mips: Add delayed branch state to insn_startRichard Henderson2-1/+3
Reviewed-by: Aurelien Jarno <aurelien@aurel32.net> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <rth@twiddle.net>
2015-10-07target-i386: Add cc_op state to insn_startRichard Henderson2-1/+2
Reviewed-by: Aurelien Jarno <aurelien@aurel32.net> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <rth@twiddle.net>
2015-10-07target-arm: Add condexec state to insn_startRichard Henderson3-2/+4
Reviewed-by: Aurelien Jarno <aurelien@aurel32.net> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <rth@twiddle.net>
2015-10-07tcg: Allow extra data to be attached to insn_startRichard Henderson4-16/+59
With an eye toward having this data replace the gen_opc_* arrays that each target collects in order to enable restore_state_from_tb. Reviewed-by: Aurelien Jarno <aurelien@aurel32.net> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <rth@twiddle.net>
2015-10-07target-*: Introduce and use cpu_breakpoint_testRichard Henderson18-239/+160
Reduce the boilerplate required for each target. At the same time, move the test for breakpoint after calling tcg_gen_insn_start. Note that arm and aarch64 do not use cpu_breakpoint_test, but still move the inline test down after tcg_gen_insn_start. Reviewed-by: Aurelien Jarno <aurelien@aurel32.net> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <rth@twiddle.net>
2015-10-07target-*: Increment num_insns immediately after tcg_gen_insn_startRichard Henderson19-39/+41
This does tidy the icount test common to all targets. Reviewed-by: Aurelien Jarno <aurelien@aurel32.net> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <rth@twiddle.net>
2015-10-07target-*: Unconditionally emit tcg_gen_insn_startRichard Henderson20-81/+41
While we're at it, emit the opcode adjacent to where we currently record data for search_pc. This puts gen_io_start et al on the "correct" side of the marker. Reviewed-by: Aurelien Jarno <aurelien@aurel32.net> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <rth@twiddle.net>
2015-10-07tcg: Rename debug_insn_start to insn_startRichard Henderson23-37/+28
With an eye toward making it mandatory. Reviewed-by: Aurelien Jarno <aurelien@aurel32.net> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <rth@twiddle.net>
2015-10-07target-tilegx: Support iret instruction and related special registersChen Gang4-1/+38
EX_CONTEXT_0_0 is used for jumping address, and EX_CONTEXT_0_1 is for INTERRUPT_CRITICAL_SECTION, which should only be 0 or 1 in user mode, or it will cause target SIGILL (and the patch doesn't support system mode). Signed-off-by: Chen Gang <gang.chen.5i5j@gmail.com> Signed-off-by: Richard Henderson <rth@twiddle.net>
2015-10-07target-tilegx: Use TILEGX_EXCP_OPCODE_UNKNOWN and ↵Chen Gang1-17/+24
TILEGX_EXCP_OPCODE_UNIMPLEMENTED correctly For some cases, they are for TILEGX_EXCP_OPCODE_UNKNOWN, not for TILEGX_EXCP_OPCODE_UNIMPLEMENTED. Also for some cases, they are for TILEGX_EXCP_OPCODE_UNIMPLEMENTED, not for TILEGX_EXCP_OPCODE_UNKNOWN. When analyzing issues, the correct printing information is necessary, e.g. grep UIMP in gcc testsuite output log for finding qemu tilegx umimplementation issues, grep UNKNOWN for finding unknown instructions. Signed-off-by: Chen Gang <gang.chen.5i5j@gmail.com> Signed-off-by: Richard Henderson <rth@twiddle.net>
2015-10-07target-tilegx: Implement v2mults instructionChen Gang3-0/+20
Signed-off-by: Chen Gang <gang.chen.5i5j@gmail.com> Message-Id: <1443956491-26850-3-git-send-email-gang.chen.5i5j@gmail.com> Signed-off-by: Richard Henderson <rth@twiddle.net>
2015-10-07target-tilegx: Implement v?int_* instructions.Chen Gang3-0/+67
Signed-off-by: Chen Gang <gang.chen.5i5j@gmail.com> Message-Id: <1443956491-26850-2-git-send-email-gang.chen.5i5j@gmail.com> Signed-off-by: Richard Henderson <rth@twiddle.net>
2015-10-07target-tilegx: Implement v2sh* instructionsChen Gang1-1/+17
It is just according to v1sh* instructions implementation. Signed-off-by: Chen Gang <gang.chen.5i5j@gmail.com> Message-Id: <1443956491-26850-1-git-send-email-gang.chen.5i5j@gmail.com> Signed-off-by: Richard Henderson <rth@twiddle.net>
2015-10-07target-tilegx: Handle nofault prefetch instructionsRichard Henderson1-14/+26
These are mapped onto some of the normal load instructions, when the destination is the zero register. Other load insns do fault even when targeting the zero register. Signed-off-by: Richard Henderson <rth@twiddle.net>
2015-10-07target-tilegx: Fix a typo for mnemonic about "ld_add"Chen Gang1-1/+1
Signed-off-by: Chen Gang <gang.chen.5i5j@gmail.com> Message-Id: <1443562720-3008-1-git-send-email-gang.chen.5i5j@gmail.com> Signed-off-by: Richard Henderson <rth@twiddle.net>
2015-10-07target-tilegx: Use TILEGX_EXCP_SIGNAL instead of TILEGX_EXCP_SEGVRichard Henderson3-21/+30
Consolidate signal handling under a single exception. Signed-off-by: Richard Henderson <rth@twiddle.net>
2015-10-07target-tilegx: Decode ill pseudo-instructionsChen Gang3-15/+85
Notice raise and bpt, decoding the constants embedded in the nop addil instruction in the x0 slot. [rth: Generalize TILEGX_EXCP_OPCODE_ILL to TILEGX_EXCP_SIGNAL. Drop validation of signal values.] Signed-off-by: Chen Gang <gang.chen.5i5j@gmail.com> Message-Id: <1443243635-4886-1-git-send-email-gang.chen.5i5j@gmail.com> Signed-off-by: Richard Henderson <rth@twiddle.net>
2015-10-07linux-user/tilegx: Implement tilegx signal featuresChen Gang2-1/+161
[rth: Remove the spreg[EX1] handling, as it's irrelevant to user-mode.] Signed-off-by: Chen Gang <gang.chen.5i5j@gmail.com> Message-Id: <1443312618-13641-1-git-send-email-gang.chen.5i5j@gmail.com> Signed-off-by: Richard Henderson <rth@twiddle.net>
2015-10-07linux-user/syscall_defs.h: Sync the latest si_code from Linux kernelChen Gang1-0/+11
They content several new macro members, also contents TARGET_N*. Signed-off-by: Chen Gang <gang.chen.5i5j@gmail.com> Message-Id: <1443240605-2924-1-git-send-email-gang.chen.5i5j@gmail.com> Signed-off-by: Richard Henderson <rth@twiddle.net>
2015-10-07target-tilegx: Let x1 pipe process bpt instruction onlyChen Gang1-1/+7
According to the related document, bpt can be only in x1 pipe. Signed-off-by: Chen Gang <gang.chen.5i5j@gmail.com> Message-Id: <1443224574-2718-1-git-send-email-gang.chen.5i5j@gmail.com> Signed-off-by: Richard Henderson <rth@twiddle.net>
2015-10-07target-tilegx: Implement complex multiply instructionsRichard Henderson3-1/+73
Signed-off-by: Richard Henderson <rth@twiddle.net>
2015-10-07target-tilegx: Implement table index instructionsRichard Henderson1-0/+15
Signed-off-by: Richard Henderson <rth@twiddle.net>
2015-10-07target-tilegx: Implement crc instructionsRichard Henderson3-1/+28
Signed-off-by: Richard Henderson <rth@twiddle.net>
2015-10-07target-tilegx: Implement v1multu instructionChen Gang3-0/+18
Signed-off-by: Chen Gang <gang.chen.5i5j@gmail.com> Reviewed-by: Richard Henderson <rth@twiddle.net> Message-Id: <1442874414-3578-1-git-send-email-gang.chen.5i5j@gmail.com> Signed-off-by: Richard Henderson <rth@twiddle.net>
2015-10-07target-tilegx: Implement v*add and v*sub instructionsChen Gang1-21/+116
[rth: Implement everything inline; handle v1addi and v2addi as well.] Signed-off-by: Chen Gang <gang.chen.5i5j@gmail.com> Message-Id: <1442873918-3394-1-git-send-email-gang.chen.5i5j@gmail.com> Signed-off-by: Richard Henderson <rth@twiddle.net>
2015-10-07target-tilegx: Implement v*shl, v*shru, and v*shrs instructionsChen Gang3-0/+73
v2sh* are implemented with helper functions; v4sh* are implmeneted with inline code. Signed-off-by: Chen Gang <gang.chen.5i5j@gmail.com> Message-Id: <1442872055-2836-1-git-send-email-gang.chen.5i5j@gmail.com> Signed-off-by: Richard Henderson <rth@twiddle.net>
2015-10-07target-tilegx: Tidy simd_helper.cRichard Henderson1-4/+7
Using the V1 macro when we want to replicate a byte across the 8 elements of the word. Using deposit and extract for manipulating specific elements. Signed-off-by: Richard Henderson <rth@twiddle.net>
2015-10-06pc-dimm: Fail realization for invalid nodes in non-NUMA configBharata B Rao1-2/+3
pc_dimm_realize() validates the NUMA node to which memory hotplug is being performed only in case of NUMA configuration. Include a check to fail for invalid nodes in case of non-NUMA configuration too. Signed-off-by: Bharata B Rao <bharata@linux.vnet.ibm.com> Reviewed-by: David Gibson <david@gibson.dropbear.id.au> Reviewed-by: Igor Mammedov <imammedo@redhat.com> Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
2015-10-06Merge remote-tracking branch 'remotes/borntraeger/tags/s390x-20151006' into ↵Peter Maydell9-17/+118
staging s390: fixes Some fixes all over the place: - ccw bios and gcc 5.1 (avoid floating point ops) - properly print vector registers - sclp and sclp-event-facility no longer hang on object_unref(object_new(T)) - better name for io_subsystem_reset One feature - the gdb server now exposes several virtualization specific register # gpg: Signature made Tue 06 Oct 2015 11:20:24 BST using RSA key ID B5A61C7C # gpg: Good signature from "Christian Borntraeger (IBM) <borntraeger@de.ibm.com>" * remotes/borntraeger/tags/s390x-20151006: s390x: rename io_subsystem_reset -> subsystem_reset s390x/info registers: print vector registers properly s390x: set missing parent for hotplug and quiesce events s390x/gdb: expose virtualization specific registers pc-bios/s390-ccw: avoid floating point operations Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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