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2012-06-20target-arm: Move block cache ops to new cp15 frameworkPeter Maydell2-6/+14
Move the v6 optional block cache ops to the new cp15 framework. This includes only providing them on the CPUs which implemented them, rather than the previous blunderbuss approach of making all MCRR instructions on all CPUs act as NOPs. Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2012-06-20target-arm: Remove c0_cachetype CPUARMState fieldPeter Maydell2-4/+1
Remove the no-longer-used CPUARMState c0_cachetype field. Although this was a constant register we had it in our migration state. Drop this (with resulting version bump) because for ARM currently we prefer cleaner migration code and have not stabilised migration format yet. Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2012-06-20target-arm: Convert final ID registersPeter Maydell2-50/+68
Convert the final ID registers to the new cp15 scheme. Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2012-06-20target-arm: Convert MPIDRPeter Maydell3-22/+31
Convert the MPIDR to the new cp15 register scheme. This includes giving it its own feature bit rather than doing a CPUID value check. Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2012-06-20target-arm: Convert cp15 cache ID registersPeter Maydell3-32/+33
Convert the cp15 cache ID registers to the new scheme. Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2012-06-20target-arm: Convert cp15 crn=0 crm={1,2} feature registersPeter Maydell3-24/+54
Convert the cp15 crn=0 crm={1,2} features registers to the new cp reg framework. Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2012-06-20target-arm: Convert cp15 crn=1 registersPeter Maydell3-76/+61
Convert the cp15 crn=1 registers to the new scheme. Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2012-06-20target-arm: Convert cp15 crn=9 registersPeter Maydell2-79/+59
Convert cp15 crn=9 registers (mostly cache lockdown) to the new scheme. Note that this change makes OMAPCP cores RAZ/WI the whole c9 space. This is a change from previous behaviour, but a return to the behaviour of commit c3d2689d when OMAP1 support was first added -- subsequent commits have clearly accidentally relegated the OMAPCP RAZ condition to only a subset of the crn=9 space when adding support for other cores. Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2012-06-20target-arm: Convert cp15 crn=6 registersPeter Maydell2-53/+45
Convert the cp15 crn=6 registers to the new scheme. Note that this includes some minor tidyup: drop an unnecessary underdecoding of op2 on OMAPCP cores, and only implement the pre-v6 c6,c0,0,1 IFAR on the 1026 and not on the other ARMv5 cores, which didn't have it. Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2012-06-20target-arm: convert cp15 crn=7 registersPeter Maydell3-11/+74
Convert the cp15 crn=7 registers to the new scheme. Note that to do this we have to distinguish some registers used on the ARM9 and ARM10 from some which are ARM1176 only. This is because the old code returned a value of 0 but always set the Z flag (by clearing env->ZF, since we store the Z flag in CPUState inverted). This is inconsistent with actual ARM CPU behaviour, which only sets flags for reads to r15 and sets them based on the top bits of the result. However it happened to work for the two common use cases for cp15 crn=7 reads: * On ARM9 and ARM10 the cache clean-and-test operations are typically done with a destination of r15 so that you can do a "loop: mrc ... ; bne loop" to keep cleaning until the cache is finally clean; always setting the Z flag means this loop terminates immediately * on ARM1176 the Cache Dirty Status Register reads as zero if the cache is dirty; returning 0 means this is correctly implemented for QEMU Since the new coprocessor register framework does the right thing of always setting flags based on the returned result for reads to r15, we need to split these up so that we can return (1<<30) for the ARM9/ARM10 registers but 0 for the ARM1176 one. This allows us to remove the nasty hack which always sets Z. Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2012-06-20target-arm: Convert cp15 VA-PA translation registersPeter Maydell1-43/+65
Convert the cp15 VA-PA translation registers (a subset of the crn=7 regs) to the new scheme. Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2012-06-20target-arm: Convert cp15 MMU TLB controlPeter Maydell1-20/+43
Convert cp15 MMU TLB control (crn=8) to new scheme. Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2012-06-20target-arm: Convert cp15 crn=15 registersPeter Maydell3-117/+126
Convert the cp15 crn=15 (implementation specific) registers to the new scheme. Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2012-06-20target-arm: Convert cp15 crn=10 registersPeter Maydell1-6/+5
We RAZ/WI the entire block of crn=10 registers. Note that this actually covers not just the implementation-defined TLB lockdown registers but also a number of v7 VMSA memory attribute registers which we would need to implement to support TEX remap. We retain the previous QEMU behaviour in this conversion, though. Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2012-06-20target-arm: Convert cp15 crn=13 registersPeter Maydell1-30/+31
Convert the cp15 crn=13 registers (FCSEIDR, CONTEXTIDR, and the ARM946 Trace Process Identifier Register). Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2012-06-20target-arm: Convert cp15 crn=2 registersPeter Maydell2-56/+33
Convert the cp15 crn=2 registers (MMU page table control, MPU cache control) to the new scheme. Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2012-06-20target-arm: Convert MMU fault status cp15 registersPeter Maydell1-81/+107
Convert the MMU fault status and MPU access permission cp15 registers to the new scheme. Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2012-06-20target-arm: Convert cp15 c3 registerPeter Maydell1-6/+12
Convert the cp15 c3 register (MMU domain access control or MPU write buffer control). NB that this is horribly underdecoded for modern cores (should be crn=3,crm=0, opc1=0,opc2=0) but this change preserves the existing QEMU behaviour. Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2012-06-20target-arm: Convert generic timer cp15 regsPeter Maydell1-12/+11
Convert the (dummy) generic timer cp15 implementation. Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2012-06-20target-arm: Convert performance monitor registersPeter Maydell3-149/+158
Convert the v7 performance monitor cp15 registers to the new scheme. Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2012-06-20target-arm: Convert TLS registersPeter Maydell2-58/+19
Convert TLS registers to the new cp15 framework Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2012-06-20target-arm: Convert WFI/barriers special cases to cp_reginfoPeter Maydell2-51/+42
Convert the various WFI and barrier instruction special cases to use cp_reginfo infrastructure. Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2012-06-20target-arm: Convert TEECR, TEEHBR to new schemePeter Maydell3-77/+45
Convert the THUMB2EE cp14 registers TEECR and TEEHBR to use arm_cp_reginfo. Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2012-06-20target-arm: Convert debug registers to cp_reginfoPeter Maydell2-28/+25
Convert the cp14 debug registers (DBGDIDR, DBGDRAR, DBGDSAR) to the cp_reginfo scheme. Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2012-06-20target-arm: Add register_cp_regs_for_features()Peter Maydell3-0/+14
Add new function register_cp_regs_for_features() as a place to register coprocessor registers dependent on feature flags. Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2012-06-20target-arm: Remove old cpu_arm_set_cp_io infrastructurePeter Maydell4-107/+1
All the users of cpu_arm_set_cp_io have been converted, so we can remove it and the infrastructure it used. Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2012-06-20hw/pxa2xx_pic: Convert coprocessor registers to new schemePeter Maydell1-22/+31
Convert the coprocessor access functions for the pxa2xx PIC to the arm_cp_reginfo scheme. Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2012-06-20hw/pxa2xx.c: Convert CLKCFG and PWRMODE cp14 regsPeter Maydell1-100/+71
Convert the PXA2xx CLKCFG and PWRMODE cp14 registers to the new arm_cp_reginfo scheme. Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2012-06-20hw/pxa2xx: Convert cp14 perf registers to new schemePeter Maydell1-81/+61
Convert the PXA2xx cp14 perf registers from old-style coprocessor hooks to the new scheme. Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2012-06-20target-arm: initial coprocessor register frameworkPeter Maydell7-3/+546
Initial infrastructure for data-driven registration of coprocessor register implementations. We still fall back to the old-style switch statements pending complete conversion of all existing registers. Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2012-06-20target-arm: Fix 11MPCore cache type register valuePeter Maydell1-1/+1
Make the 11MPCore report a valid value in its cache type register (the previous value appears to have been incorrectly copied from the 1136/1176). In particular, do not report that we have an aliasing VIPT cache, because this causes Linux to attempt to use the v6 block cache ops which the 11MPCore doesn't actually have. (This causes no problems currently because we over-broadly provide those ops on all cores, but prevents us correctly narrowing the block ops down to those cores which actually implement them.) Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2012-06-19Allow machines to configure the QEMU_VERSION that's exposed via hardwareCrístian Viana19-25/+62
QEMU exposes its version to the guest's hardware and in some cases that is wrong (e.g. Windows prints messages about driver updates when you switch the QEMU version). There is a new field now on the struct QEmuMachine, hw_version, which may contain the version that the specific machine should report. If that field is set, then that machine will report that version to the guest. Signed-off-by: Crístian Viana <vianac@linux.vnet.ibm.com> Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
2012-06-19Add PIIX4 properties to control PM system states.Gleb Natapov8-11/+32
This patch adds two things. First it allows QEMU to distinguish between regular powerdown and S4 powerdown. Later separate QMP notification will be added for S4 powerdown. Second it allows S3/S4 states to be disabled from QEMU command line. Some guests known to be broken with regards to power management, but allow to use it anyway. Using new properties management will be able to disable S3/S4 for such guests. Supported system state are passed to a firmware using new fw_cfg file. The file contains 6 byte array. Each byte represents one system state. If byte at offset X has its MSB set it means that system state X is supported and to enter it guest should use the value from lowest 3 bits. Signed-off-by: Gleb Natapov <gleb@redhat.com> Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
2012-06-19make: automatically include dependencies in recursive subdir rules (v2)Anthony Liguori7-6/+8
I think I understand enough of what's going on in these rules to ensure this is right. But I could certainly use a second or third opinion... Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
2012-06-19configure: fix -enable-debug with newer toolchainsAvi Kivity1-2/+1
Fedora 17's toolchain wants optimization enabled for _FORTIFY_SOURCE; so disable _FORTIFY_SOURCE when debugging. Signed-off-by: Avi Kivity <avi@redhat.com> Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
2012-06-18Merge remote-tracking branch 'afaerber-or/qom-next-2' into stagingAnthony Liguori41-503/+869
* afaerber-or/qom-next-2: (22 commits) qom: Push error reporting to object_property_find() qdev: Remove qdev_prop_exists() qbus: Initialize in standard way qbus: Make child devices links qdev: Connect busses with their parent devices qdev: Convert busses to QEMU Object Model qdev: Move SysBus initialization to sysbus.c qdev: Use wrapper for qdev_get_path qdev: Remove qdev_prop_set_defaults qdev: Clean up global properties qdev: Move bus properties to abstract superclasses qdev: Move bus properties to a separate global qdev: Push "type" property up to Object arm_l2x0: Rename "type" property to "cache-type" m48t59: Rename "type" property to "model" qom: Assert that public types have a non-NULL parent field qom: Drop type_register_static_alias() macro qom: Make Object a type qom: Add class_base_init qom: Add object_child_foreach() ...
2012-06-18Merge remote-tracking branch 'qmp/queue/qmp' into stagingAnthony Liguori12-9/+204
* qmp/queue/qmp: build: install qmp-commands.txt Add rate limiting of RTC_CHANGE, BALLOON_CHANGE & WATCHDOG events Add event notification for guest balloon changes Fix some more license versions (GPL2+ instead of GPL2) monitor: Fix memory leak with readline completion qmp: do not include monitor.h from qapi-types-core.h qmp: include monitor.h when needed kvm: add missing include files
2012-06-18Merge remote-tracking branch 'kwolf/for-anthony' into stagingAnthony Liguori45-243/+2531
* kwolf/for-anthony: (39 commits) qemu-iotests: add 036 autoclear feature bit test qemu-iotests: add qcow2.py set-feature-bit command fdc-test: introduced qtest read_without_media fdc: fix implied seek while there is no media in drive qcow2: fix autoclear image header update xen: Don't peek behind the BlockDriverState abstraction xen: Don't change -drive if=xen device name during machine init block: Replace bdrv_get_format() by bdrv_get_format_name() qemu-img: document qed format on qemu-img man page qemu-iotests: COW with many AIO requests on the same cluster qemu-iotests: Some backing file COW tests qcow2: Fix avail_sectors in cluster allocation code qcow2: Simplify calculation for COW area at the end qcow2: always operate caches in writeback mode ide: support enable/disable write cache block: always open drivers in writeback mode block: add bdrv_set_enable_write_cache block: copy enable_write_cache in bdrv_append savevm: flush after saving vm state block: flush in writethrough mode after writes ...
2012-06-18Merge remote-tracking branch 'mst/tags/for_anthony' into stagingAnthony Liguori17-66/+61
* mst/tags/for_anthony: pci_bridge_dev: fix error path in pci_bridge_dev_initfn() qdev: release parent properties on dc->init failure msi: Use msi/msix_present more consistently msi: Invoke msi/msix_write_config from PCI core msi: Guard msi/msix_write_config with msi_present msi: Invoke msi/msix_reset from PCI core msi: Guard msi_reset with msi_present ahci: Clean up reset functions intel-hda: Fix reset of MSI function ahci: Fix reset of MSI function rtl8139: honor RxOverflow flag in can_receive method shpc: unparent device before free
2012-06-18Merge remote-tracking branch 'sweil/for-anthony' into stagingAnthony Liguori10-16/+23
* sweil/for-anthony: Fix some more license versions (GPL2+ instead of GPL2) dump: Fix license version (GPL2+ instead of GPL2) configure: Fix build for some versions of glibc (9pfs) monitor: Fix memory leak with readline completion
2012-06-18qom: Push error reporting to object_property_find()Paolo Bonzini4-17/+13
Avoids duplicated error_set(). Signed-off-by: Paolo Bonzini <pbonzini@redhat.com> [AF: Also drop error_set() in object_property_del().] Signed-off-by: Andreas Färber <afaerber@suse.de>
2012-06-18qdev: Remove qdev_prop_exists()Paolo Bonzini6-9/+12
Can be replaced everywhere with object_property_find(). Signed-off-by: Paolo Bonzini <pbonzini@redhat.com> Signed-off-by: Andreas Färber <afaerber@suse.de>
2012-06-18qbus: Initialize in standard wayAnthony Liguori1-32/+48
Move code to an initfn and finalizer. Replace do_qbus_create_inplace() with qbus_realize(). Signed-off-by: Anthony Liguori <aliguori@us.ibm.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com> Signed-off-by: Andreas Färber <afaerber@suse.de>
2012-06-18qbus: Make child devices linksAnthony Liguori15-83/+159
Make qbus children show up as link<> properties. There is no stable addressing for qbus children so we use an unstable naming convention. This is okay in QOM though because the composition name is expected to be what's stable. Signed-off-by: Anthony Liguori <aliguori@us.ibm.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com> Signed-off-by: Andreas Färber <afaerber@suse.de>
2012-06-18qdev: Connect busses with their parent devicesAnthony Liguori2-0/+7
This makes SysBus part of the root hierarchy and all busses children of their respective parent DeviceState. Signed-off-by: Anthony Liguori <aliguori@us.ibm.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com> Signed-off-by: Andreas Färber <afaerber@suse.de>
2012-06-18qdev: Convert busses to QEMU Object ModelAnthony Liguori27-142/+299
This is far less interesting than it sounds. We simply add an Object to each BusState and then register the types appropriately. Most of the interesting refactoring will follow in the next patches. Since we're changing fundamental type names (BusInfo -> BusClass), it all needs to convert at once. Fortunately, not a lot of code is affected. Signed-off-by: Anthony Liguori <aliguori@us.ibm.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com> [AF: Made all new bus TypeInfos static const.] [AF: Made qbus_free() call object_delete(), required {qom,glib}_allocated] Signed-off-by: Andreas Färber <afaerber@suse.de>
2012-06-18qdev: Move SysBus initialization to sysbus.cPaolo Bonzini2-24/+23
TYPE_SYSTEM_BUS will be local to hw/sysbus.c, so move existing references to main_system_bus and system_bus_info there. Signed-off-by: Paolo Bonzini <pbonzini@redhat.com> Signed-off-by: Andreas Färber <afaerber@suse.de>
2012-06-18qdev: Use wrapper for qdev_get_pathAnthony Liguori7-17/+33
This makes it easier to remove it from BusInfo. Signed-off-by: Anthony Liguori <aliguori@us.ibm.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com> [AF: Drop now unnecessary NULL initialization in scsibus_get_dev_path()] Signed-off-by: Andreas Färber <afaerber@suse.de>
2012-06-18qdev: Remove qdev_prop_set_defaultsPaolo Bonzini3-26/+23
Instead, qdev_property_add_static can set the default. Signed-off-by: Paolo Bonzini <pbonzini@redhat.com> Reviewed-by: Anthony Liguori <aliguori@us.ibm.com> Signed-off-by: Andreas Färber <afaerber@suse.de>
2012-06-18qdev: Clean up global propertiesPaolo Bonzini2-2/+1
Now that global properties do not depend on buses anymore, set them directly in the device instance_init function. Signed-off-by: Paolo Bonzini <pbonzini@redhat.com> Signed-off-by: Andreas Färber <afaerber@suse.de>
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