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| author | Aurelien Jarno <aurelien@aurel32.net> | 2013-08-28 13:51:40 +0200 |
|---|---|---|
| committer | Aurelien Jarno <aurelien@aurel32.net> | 2013-09-03 01:34:46 +0200 |
| commit | df81ff51d50b22c52e609e13d5292d09e4634659 (patch) | |
| tree | 27ca8ea1b9f4c87bad165c9aa32add796442a14c /tcg | |
| parent | 988902fc3bc599f7431461b790f3d63d3a2357f9 (diff) | |
| download | qemu-df81ff51d50b22c52e609e13d5292d09e4634659.tar.gz qemu-df81ff51d50b22c52e609e13d5292d09e4634659.tar.bz2 qemu-df81ff51d50b22c52e609e13d5292d09e4634659.zip | |
tcg/mips: inline bswap16/bswap32 ops
Use an inline version for the bswap16 and bswap32 ops to avoid
testing for MIPS32R2 instructions availability, as these ops are
only available in that case.
Reviewed-by: Richard Henderson <rth@twiddle.net>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
Diffstat (limited to 'tcg')
| -rw-r--r-- | tcg/mips/tcg-target.c | 7 |
1 files changed, 3 insertions, 4 deletions
diff --git a/tcg/mips/tcg-target.c b/tcg/mips/tcg-target.c index 9b518c28f6..daaf722471 100644 --- a/tcg/mips/tcg-target.c +++ b/tcg/mips/tcg-target.c @@ -1506,13 +1506,12 @@ static inline void tcg_out_op(TCGContext *s, TCGOpcode opc, } break; - /* The bswap routines do not work on non-R2 CPU. In that case - we let TCG generating the corresponding code. */ case INDEX_op_bswap16_i32: - tcg_out_bswap16(s, args[0], args[1]); + tcg_out_opc_reg(s, OPC_WSBH, args[0], 0, args[1]); break; case INDEX_op_bswap32_i32: - tcg_out_bswap32(s, args[0], args[1]); + tcg_out_opc_reg(s, OPC_WSBH, args[0], 0, args[1]); + tcg_out_opc_sa(s, OPC_ROTR, args[0], args[0], 16); break; case INDEX_op_ext8s_i32: |