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authorRichard Henderson <rth@twiddle.net>2014-08-06 11:48:48 -0700
committerRichard Henderson <rth@redhat.com>2014-09-29 14:55:27 -0400
commit90379ca84ebe94b0adc08794d90ea1e196b2a724 (patch)
treec55ace94c6a479b4ecf8f01042553d5712aaa93c /tcg/sparc/tcg-target.h
parent609ac1e16473e7dfc4dc54becde4b1902dbdf919 (diff)
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tcg-sparc: Use ADDXC in addsub2_i64
On T4 and newer Sparc chips we have an add-with-carry insn that takes its input from %xcc instead of %icc. Signed-off-by: Richard Henderson <rth@twiddle.net>
Diffstat (limited to 'tcg/sparc/tcg-target.h')
-rw-r--r--tcg/sparc/tcg-target.h6
1 files changed, 6 insertions, 0 deletions
diff --git a/tcg/sparc/tcg-target.h b/tcg/sparc/tcg-target.h
index a44d34f6f7..099b3080bf 100644
--- a/tcg/sparc/tcg-target.h
+++ b/tcg/sparc/tcg-target.h
@@ -85,6 +85,12 @@ typedef enum {
#define TCG_TARGET_EXTEND_ARGS 1
#endif
+#if defined(__VIS__) && __VIS__ >= 0x300
+#define use_vis3_instructions 1
+#else
+extern bool use_vis3_instructions;
+#endif
+
/* optional instructions */
#define TCG_TARGET_HAS_div_i32 1
#define TCG_TARGET_HAS_rem_i32 0