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author | Aurelien Jarno <aurelien@aurel32.net> | 2016-04-21 10:48:49 +0200 |
---|---|---|
committer | Peter Maydell <peter.maydell@linaro.org> | 2016-04-21 15:41:47 +0100 |
commit | eabb7b91b36b202b4dac2df2d59d698e3aff197a (patch) | |
tree | 396e93ab6764d975f7c2492f995e1c6462fae3f8 /tcg/ppc | |
parent | b4850e5ae9607f9f31932f693ca48f52619493d7 (diff) | |
download | qemu-eabb7b91b36b202b4dac2df2d59d698e3aff197a.tar.gz qemu-eabb7b91b36b202b4dac2df2d59d698e3aff197a.tar.bz2 qemu-eabb7b91b36b202b4dac2df2d59d698e3aff197a.zip |
tcg: use tcg_debug_assert instead of assert (fix performance regression)
The TCG code is quite performance sensitive, but at the same time can
also be quite tricky. That is why asserts that can be enabled with the
--enable-debug-tcg configure option.
This used to work the following way:
| #include "config.h"
|
| ...
|
| #if !defined(CONFIG_DEBUG_TCG) && !defined(NDEBUG)
| /* define it to suppress various consistency checks (faster) */
| #define NDEBUG
| #endif
|
| ...
|
| #include <assert.h>
Since commit 757e725b (tcg: Clean up includes) "config.h" as been
replaced by "qemu/osdep.h" which itself includes <assert.h>. As a
consequence the assertions are always enabled, even when using
--disable-debug-tcg, causing a performance regression, especially on
targets with many registers. For instance on qemu-system-ppc the
speed difference is about 15%.
tcg_debug_assert is controlled directly by CONFIG_DEBUG_TCG and already
uses in some places. This patch replaces all the calls to assert into
calss to tcg_debug_assert.
Cc: Peter Maydell <peter.maydell@linaro.org>
Cc: Richard Henderson <rth@twiddle.net>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
Message-id: 1461228530-14852-1-git-send-email-aurelien@aurel32.net
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Diffstat (limited to 'tcg/ppc')
-rw-r--r-- | tcg/ppc/tcg-target.inc.c | 22 |
1 files changed, 11 insertions, 11 deletions
diff --git a/tcg/ppc/tcg-target.inc.c b/tcg/ppc/tcg-target.inc.c index 8c1c2dfa9b..60bcaa7f5b 100644 --- a/tcg/ppc/tcg-target.inc.c +++ b/tcg/ppc/tcg-target.inc.c @@ -207,7 +207,7 @@ static inline bool in_range_b(tcg_target_long target) static uint32_t reloc_pc24_val(tcg_insn_unit *pc, tcg_insn_unit *target) { ptrdiff_t disp = tcg_ptr_byte_diff(target, pc); - assert(in_range_b(disp)); + tcg_debug_assert(in_range_b(disp)); return disp & 0x3fffffc; } @@ -219,7 +219,7 @@ static void reloc_pc24(tcg_insn_unit *pc, tcg_insn_unit *target) static uint16_t reloc_pc14_val(tcg_insn_unit *pc, tcg_insn_unit *target) { ptrdiff_t disp = tcg_ptr_byte_diff(target, pc); - assert(disp == (int16_t) disp); + tcg_debug_assert(disp == (int16_t) disp); return disp & 0xfffc; } @@ -245,7 +245,7 @@ static void patch_reloc(tcg_insn_unit *code_ptr, int type, { tcg_insn_unit *target = (tcg_insn_unit *)value; - assert(addend == 0); + tcg_debug_assert(addend == 0); switch (type) { case R_PPC_REL14: reloc_pc14(code_ptr, target); @@ -565,7 +565,7 @@ static void tcg_out_mov(TCGContext *s, TCGType type, TCGReg ret, TCGReg arg) static inline void tcg_out_rld(TCGContext *s, int op, TCGReg ra, TCGReg rs, int sh, int mb) { - assert(TCG_TARGET_REG_BITS == 64); + tcg_debug_assert(TCG_TARGET_REG_BITS == 64); sh = SH(sh & 0x1f) | (((sh >> 5) & 1) << 1); mb = MB64((mb >> 5) | ((mb << 1) & 0x3f)); tcg_out32(s, op | RA(ra) | RS(rs) | sh | mb); @@ -718,7 +718,7 @@ static void tcg_out_andi64(TCGContext *s, TCGReg dst, TCGReg src, uint64_t c) { int mb, me; - assert(TCG_TARGET_REG_BITS == 64); + tcg_debug_assert(TCG_TARGET_REG_BITS == 64); if (mask64_operand(c, &mb, &me)) { if (mb == 0) { tcg_out_rld(s, RLDICR, dst, src, 0, me); @@ -834,7 +834,7 @@ static inline void tcg_out_ld(TCGContext *s, TCGType type, TCGReg ret, { int opi, opx; - assert(TCG_TARGET_REG_BITS == 64 || type == TCG_TYPE_I32); + tcg_debug_assert(TCG_TARGET_REG_BITS == 64 || type == TCG_TYPE_I32); if (type == TCG_TYPE_I32) { opi = LWZ, opx = LWZX; } else { @@ -848,7 +848,7 @@ static inline void tcg_out_st(TCGContext *s, TCGType type, TCGReg arg, { int opi, opx; - assert(TCG_TARGET_REG_BITS == 64 || type == TCG_TYPE_I32); + tcg_debug_assert(TCG_TARGET_REG_BITS == 64 || type == TCG_TYPE_I32); if (type == TCG_TYPE_I32) { opi = STW, opx = STWX; } else { @@ -981,7 +981,7 @@ static void tcg_out_setcond(TCGContext *s, TCGType type, TCGCond cond, { int crop, sh; - assert(TCG_TARGET_REG_BITS == 64 || type == TCG_TYPE_I32); + tcg_debug_assert(TCG_TARGET_REG_BITS == 64 || type == TCG_TYPE_I32); /* Ignore high bits of a potential constant arg2. */ if (type == TCG_TYPE_I32) { @@ -1251,11 +1251,11 @@ void ppc_tb_set_jmp_target(uintptr_t jmp_addr, uintptr_t addr) diff = addr - (uintptr_t)tb_ret_addr; lo = (int16_t)diff; hi = (int32_t)(diff - lo); - assert(diff == hi + lo); + tcg_debug_assert(diff == hi + lo); i1 = ADDIS | TAI(TCG_REG_TMP1, TCG_REG_RA, hi >> 16); i2 = ADDI | TAI(TCG_REG_TMP1, TCG_REG_TMP1, lo); } else { - assert(TCG_TARGET_REG_BITS == 32 || addr == (int32_t)addr); + tcg_debug_assert(TCG_TARGET_REG_BITS == 32 || addr == (int32_t)addr); i1 = ADDIS | TAI(TCG_REG_TMP1, 0, addr >> 16); i2 = ORI | SAI(TCG_REG_TMP1, TCG_REG_TMP1, addr); } @@ -1857,7 +1857,7 @@ static void tcg_target_qemu_prologue(TCGContext *s) } /* Epilogue */ - assert(tb_ret_addr == s->code_ptr); + tcg_debug_assert(tb_ret_addr == s->code_ptr); tcg_out_ld(s, TCG_TYPE_PTR, TCG_REG_R0, TCG_REG_R1, FRAME_SIZE+LR_OFFSET); for (i = 0; i < ARRAY_SIZE(tcg_target_callee_save_regs); ++i) { |