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| author | Richard Henderson <rth@twiddle.net> | 2013-08-14 15:03:27 -0700 |
|---|---|---|
| committer | Richard Henderson <rth@twiddle.net> | 2014-03-14 11:00:07 -0700 |
| commit | 1fcc9ddfb3c42431c027eb490613b51491202daa (patch) | |
| tree | 4ef349c9c107f21ea426b8f634aff500dd3698b2 /tcg/aarch64/tcg-target.c | |
| parent | c6e929e7847cb440dbda8ae562a1fb1fdc5f0c77 (diff) | |
| download | qemu-1fcc9ddfb3c42431c027eb490613b51491202daa.tar.gz qemu-1fcc9ddfb3c42431c027eb490613b51491202daa.tar.bz2 qemu-1fcc9ddfb3c42431c027eb490613b51491202daa.zip | |
tcg-aarch64: Support muluh, mulsh
Signed-off-by: Richard Henderson <rth@twiddle.net>
Reviewed-by: Claudio Fontana <claudio.fontana@huawei.com>
Tested-by: Claudio Fontana <claudio.fontana@huawei.com>
Diffstat (limited to 'tcg/aarch64/tcg-target.c')
| -rw-r--r-- | tcg/aarch64/tcg-target.c | 12 |
1 files changed, 12 insertions, 0 deletions
diff --git a/tcg/aarch64/tcg-target.c b/tcg/aarch64/tcg-target.c index b9dc6bb67b..9c5082018a 100644 --- a/tcg/aarch64/tcg-target.c +++ b/tcg/aarch64/tcg-target.c @@ -311,6 +311,8 @@ typedef enum { I3508_LSRV = 0x1ac02400, I3508_ASRV = 0x1ac02800, I3508_RORV = 0x1ac02c00, + I3508_SMULH = 0x9b407c00, + I3508_UMULH = 0x9bc07c00, /* Logical shifted register instructions (without a shift). */ I3510_AND = 0x0a000000, @@ -1565,6 +1567,13 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, args[5], const_args[4], const_args[5], true); break; + case INDEX_op_muluh_i64: + tcg_out_insn(s, 3508, UMULH, TCG_TYPE_I64, a0, a1, a2); + break; + case INDEX_op_mulsh_i64: + tcg_out_insn(s, 3508, SMULH, TCG_TYPE_I64, a0, a1, a2); + break; + case INDEX_op_mov_i64: case INDEX_op_mov_i32: case INDEX_op_movi_i64: @@ -1694,6 +1703,9 @@ static const TCGTargetOpDef aarch64_op_defs[] = { { INDEX_op_sub2_i32, { "r", "r", "rZ", "rZ", "rwA", "rwMZ" } }, { INDEX_op_sub2_i64, { "r", "r", "rZ", "rZ", "rA", "rMZ" } }, + { INDEX_op_muluh_i64, { "r", "r", "r" } }, + { INDEX_op_mulsh_i64, { "r", "r", "r" } }, + { -1 }, }; |