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| author | Max Filippov <jcmvbkbc@gmail.com> | 2012-12-05 07:15:22 +0400 |
|---|---|---|
| committer | Blue Swirl <blauwirbel@gmail.com> | 2012-12-08 18:48:26 +0000 |
| commit | fe0bd475aa31e60674f7f53b85dc293108026202 (patch) | |
| tree | e67f93a3470a0738eed141ebe5633872416b31a2 /target-xtensa/cpu.h | |
| parent | 4e41d2f5830a76d3fe92b3d3b18cc9f2ee927770 (diff) | |
| download | qemu-fe0bd475aa31e60674f7f53b85dc293108026202.tar.gz qemu-fe0bd475aa31e60674f7f53b85dc293108026202.tar.bz2 qemu-fe0bd475aa31e60674f7f53b85dc293108026202.zip | |
target-xtensa: restrict available SRs by enabled options
Beginning with the RA-2004.1 release, SR access instructions (rsr, wsr,
xsr) are associated with their corresponding SR and raise illegal opcode
exception in case the register is not configured for the core.
Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
Diffstat (limited to 'target-xtensa/cpu.h')
| -rw-r--r-- | target-xtensa/cpu.h | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/target-xtensa/cpu.h b/target-xtensa/cpu.h index 068ad69ee9..a73d32d898 100644 --- a/target-xtensa/cpu.h +++ b/target-xtensa/cpu.h @@ -416,6 +416,7 @@ void debug_exception_env(CPUXtensaState *new_env, uint32_t cause); #define XTENSA_OPTION_BIT(opt) (((uint64_t)1) << (opt)) +#define XTENSA_OPTION_ALL (~(uint64_t)0) static inline bool xtensa_option_bits_enabled(const XtensaConfig *config, uint64_t opt) |