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| author | Aurelien Jarno <aurelien@aurel32.net> | 2010-02-02 19:39:11 +0100 |
|---|---|---|
| committer | Aurelien Jarno <aurelien@aurel32.net> | 2010-02-09 21:07:03 +0100 |
| commit | d4b851cb45de4de8166fb29e34c6bd5c39e0dda8 (patch) | |
| tree | 966a3463050e3ea20ff252e85412b3e176bceb80 /target-sh4 | |
| parent | 47ae41fbdfa5f84d6a7921c8fd2627f74a782d86 (diff) | |
| download | qemu-d4b851cb45de4de8166fb29e34c6bd5c39e0dda8.tar.gz qemu-d4b851cb45de4de8166fb29e34c6bd5c39e0dda8.tar.bz2 qemu-d4b851cb45de4de8166fb29e34c6bd5c39e0dda8.zip | |
sh7750: handle MMUCR TI bit
When the MMUCR TI bit is set, all the UTLB and ITLB entries should be
flushed.
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
Diffstat (limited to 'target-sh4')
| -rw-r--r-- | target-sh4/cpu.h | 2 | ||||
| -rw-r--r-- | target-sh4/helper.c | 18 |
2 files changed, 20 insertions, 0 deletions
diff --git a/target-sh4/cpu.h b/target-sh4/cpu.h index 366e7986ed..015d59845a 100644 --- a/target-sh4/cpu.h +++ b/target-sh4/cpu.h @@ -167,6 +167,7 @@ int cpu_sh4_handle_mmu_fault(CPUSH4State * env, target_ulong address, int rw, void do_interrupt(CPUSH4State * env); void sh4_cpu_list(FILE *f, int (*cpu_fprintf)(FILE *f, const char *fmt, ...)); +void cpu_sh4_invalidate_tlb(CPUSH4State *s); void cpu_sh4_write_mmaped_utlb_addr(CPUSH4State *s, target_phys_addr_t addr, uint32_t mem_value); @@ -222,6 +223,7 @@ enum { /* MMU control register */ #define MMUCR 0x1F000010 #define MMUCR_AT (1<<0) +#define MMUCR_TI (1<<2) #define MMUCR_SV (1<<8) #define MMUCR_URC_BITS (6) #define MMUCR_URC_OFFSET (10) diff --git a/target-sh4/helper.c b/target-sh4/helper.c index 088d36a5f7..e7c494fb9a 100644 --- a/target-sh4/helper.c +++ b/target-sh4/helper.c @@ -574,6 +574,24 @@ void cpu_load_tlb(CPUSH4State * env) entry->tc = (uint8_t)cpu_ptea_tc(env->ptea); } + void cpu_sh4_invalidate_tlb(CPUSH4State *s) +{ + int i; + + /* UTLB */ + for (i = 0; i < UTLB_SIZE; i++) { + tlb_t * entry = &s->utlb[i]; + entry->v = 0; + } + /* ITLB */ + for (i = 0; i < UTLB_SIZE; i++) { + tlb_t * entry = &s->utlb[i]; + entry->v = 0; + } + + tlb_flush(s, 1); +} + void cpu_sh4_write_mmaped_utlb_addr(CPUSH4State *s, target_phys_addr_t addr, uint32_t mem_value) { |