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| author | Richard Henderson <rth@twiddle.net> | 2013-02-19 23:52:23 -0800 |
|---|---|---|
| committer | Blue Swirl <blauwirbel@gmail.com> | 2013-02-23 17:25:31 +0000 |
| commit | 1d3b708491b9d7dde573261fdee8ca0afc6980fd (patch) | |
| tree | f70d9577c9571a6c2560c897fcf5bd20bed8d30f /target-sh4 | |
| parent | 528692a8a4fb6c545d818957e758d6ad70fa255c (diff) | |
| download | qemu-1d3b708491b9d7dde573261fdee8ca0afc6980fd.tar.gz qemu-1d3b708491b9d7dde573261fdee8ca0afc6980fd.tar.bz2 qemu-1d3b708491b9d7dde573261fdee8ca0afc6980fd.zip | |
target-sh4: Use mul*2 for dmul*
Cc: Aurelien Jarno <aurelien@aurel32.net>
Signed-off-by: Richard Henderson <rth@twiddle.net>
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
Diffstat (limited to 'target-sh4')
| -rw-r--r-- | target-sh4/translate.c | 30 |
1 files changed, 2 insertions, 28 deletions
diff --git a/target-sh4/translate.c b/target-sh4/translate.c index c58d79a5cd..d255066e0a 100644 --- a/target-sh4/translate.c +++ b/target-sh4/translate.c @@ -833,36 +833,10 @@ static void _decode_opc(DisasContext * ctx) gen_helper_div1(REG(B11_8), cpu_env, REG(B7_4), REG(B11_8)); return; case 0x300d: /* dmuls.l Rm,Rn */ - { - TCGv_i64 tmp1 = tcg_temp_new_i64(); - TCGv_i64 tmp2 = tcg_temp_new_i64(); - - tcg_gen_ext_i32_i64(tmp1, REG(B7_4)); - tcg_gen_ext_i32_i64(tmp2, REG(B11_8)); - tcg_gen_mul_i64(tmp1, tmp1, tmp2); - tcg_gen_trunc_i64_i32(cpu_macl, tmp1); - tcg_gen_shri_i64(tmp1, tmp1, 32); - tcg_gen_trunc_i64_i32(cpu_mach, tmp1); - - tcg_temp_free_i64(tmp2); - tcg_temp_free_i64(tmp1); - } + tcg_gen_muls2_i32(cpu_macl, cpu_mach, REG(B7_4), REG(B11_8)); return; case 0x3005: /* dmulu.l Rm,Rn */ - { - TCGv_i64 tmp1 = tcg_temp_new_i64(); - TCGv_i64 tmp2 = tcg_temp_new_i64(); - - tcg_gen_extu_i32_i64(tmp1, REG(B7_4)); - tcg_gen_extu_i32_i64(tmp2, REG(B11_8)); - tcg_gen_mul_i64(tmp1, tmp1, tmp2); - tcg_gen_trunc_i64_i32(cpu_macl, tmp1); - tcg_gen_shri_i64(tmp1, tmp1, 32); - tcg_gen_trunc_i64_i32(cpu_mach, tmp1); - - tcg_temp_free_i64(tmp2); - tcg_temp_free_i64(tmp1); - } + tcg_gen_mulu2_i32(cpu_macl, cpu_mach, REG(B7_4), REG(B11_8)); return; case 0x600e: /* exts.b Rm,Rn */ tcg_gen_ext8s_i32(REG(B11_8), REG(B7_4)); |