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| author | David Gibson <david@gibson.dropbear.id.au> | 2013-04-07 19:08:19 +0000 |
|---|---|---|
| committer | Alexander Graf <agraf@suse.de> | 2013-04-26 23:02:41 +0200 |
| commit | 0cbad81f70546b58f08de3225f1eca7a8b869b09 (patch) | |
| tree | 9a0adc74e12dbbe58e60ad1f1ebcb7ce986a589c /target-ppc | |
| parent | f36951c19f15f3c053a31234bd2c297d86c1a052 (diff) | |
| download | qemu-0cbad81f70546b58f08de3225f1eca7a8b869b09.tar.gz qemu-0cbad81f70546b58f08de3225f1eca7a8b869b09.tar.bz2 qemu-0cbad81f70546b58f08de3225f1eca7a8b869b09.zip | |
pseries: Fixes and enhancements to L1 cache properties
PAPR requires that the device tree's CPU nodes have several properties
with information about the L1 cache. We already create two of these
properties, but with incorrect names - "[id]cache-block-size" instead
of "[id]-cache-block-size" (note the extra hyphen).
We were also missing some of the required cache properties. This
patch adds the [id]-cache-line-size properties (which have the same
values as the block size properties in all current cases). We also
add the [id]-cache-size properties.
Adding the cache sizes requires some extra infrastructure in the
general target-ppc code to (optionally) set the cache sizes for
various CPUs. The CPU family descriptions in translate_init.c can set
these sizes - this patch adds correct information for POWER7, I'm
leaving other CPU types to people who have a physical example to
verify against. In addition, for -cpu host we take the values
advertised by the host (if available) and use those to override the
information based on PVR.
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
Signed-off-by: Alexander Graf <agraf@suse.de>
Diffstat (limited to 'target-ppc')
| -rw-r--r-- | target-ppc/cpu-qom.h | 1 | ||||
| -rw-r--r-- | target-ppc/kvm.c | 10 | ||||
| -rw-r--r-- | target-ppc/translate_init.c | 3 |
3 files changed, 14 insertions, 0 deletions
diff --git a/target-ppc/cpu-qom.h b/target-ppc/cpu-qom.h index c27cef7e32..eb03a00799 100644 --- a/target-ppc/cpu-qom.h +++ b/target-ppc/cpu-qom.h @@ -63,6 +63,7 @@ typedef struct PowerPCCPUClass { powerpc_input_t bus_model; uint32_t flags; int bfd_mach; + uint32_t l1_dcache_size, l1_icache_size; #if defined(TARGET_PPC64) const struct ppc_segment_page_sizes *sps; #endif diff --git a/target-ppc/kvm.c b/target-ppc/kvm.c index a1fa8d3ddf..4e8f448d80 100644 --- a/target-ppc/kvm.c +++ b/target-ppc/kvm.c @@ -1603,6 +1603,8 @@ static void kvmppc_host_cpu_class_init(ObjectClass *oc, void *data) PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); uint32_t vmx = kvmppc_get_vmx(); uint32_t dfp = kvmppc_get_dfp(); + uint32_t dcache_size = kvmppc_read_int_cpu_dt("d-cache-size"); + uint32_t icache_size = kvmppc_read_int_cpu_dt("i-cache-size"); /* Now fix up the class with information we can query from the host */ @@ -1615,6 +1617,14 @@ static void kvmppc_host_cpu_class_init(ObjectClass *oc, void *data) /* Only override when we know what the host supports */ alter_insns(&pcc->insns_flags2, PPC2_DFP, dfp); } + + if (dcache_size != -1) { + pcc->l1_dcache_size = dcache_size; + } + + if (icache_size != -1) { + pcc->l1_icache_size = icache_size; + } } int kvmppc_fixup_cpu(PowerPCCPU *cpu) diff --git a/target-ppc/translate_init.c b/target-ppc/translate_init.c index a9bacd219a..769f5fd65a 100644 --- a/target-ppc/translate_init.c +++ b/target-ppc/translate_init.c @@ -7004,6 +7004,7 @@ static void init_proc_POWER7 (CPUPPCState *env) init_excp_POWER7(env); env->dcache_line_size = 128; env->icache_line_size = 128; + /* Allocate hardware IRQ controller */ ppcPOWER7_irq_init(env); /* Can't find information on what this should be on reset. This @@ -7041,6 +7042,8 @@ POWERPC_FAMILY(POWER7)(ObjectClass *oc, void *data) pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE | POWERPC_FLAG_BE | POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK | POWERPC_FLAG_CFAR; + pcc->l1_dcache_size = 0x8000; + pcc->l1_icache_size = 0x8000; } #endif /* defined (TARGET_PPC64) */ |