diff options
| author | Andreas Färber <afaerber@suse.de> | 2013-06-28 23:18:47 +0200 |
|---|---|---|
| committer | Andreas Färber <afaerber@suse.de> | 2013-07-26 23:23:54 +0200 |
| commit | a0e372f0c49ac01faeaeb73a6e8f50e8ac615f34 (patch) | |
| tree | 0a87f5f9ab3ff51ef996c69ded7cfa8f97768e92 /target-openrisc | |
| parent | 19a77215f1ba966c4d37dadec45f38be789b8529 (diff) | |
| download | qemu-a0e372f0c49ac01faeaeb73a6e8f50e8ac615f34.tar.gz qemu-a0e372f0c49ac01faeaeb73a6e8f50e8ac615f34.tar.bz2 qemu-a0e372f0c49ac01faeaeb73a6e8f50e8ac615f34.zip | |
cpu: Introduce CPUState::gdb_num_regs and CPUClass::gdb_num_core_regs
CPUState::gdb_num_regs replaces num_g_regs.
CPUClass::gdb_num_core_regs replaces NUM_CORE_REGS.
Allows building gdb_register_coprocessor() for xtensa, too.
As a side effect this should fix coprocessor register numbering for SMP.
Acked-by: Michael Walle <michael@walle.cc> (for lm32)
Acked-by: Max Filippov <jcmvbkbc@gmail.com> (for xtensa)
Signed-off-by: Andreas Färber <afaerber@suse.de>
Diffstat (limited to 'target-openrisc')
| -rw-r--r-- | target-openrisc/cpu.c | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/target-openrisc/cpu.c b/target-openrisc/cpu.c index 7718820ecc..9b042e14b0 100644 --- a/target-openrisc/cpu.c +++ b/target-openrisc/cpu.c @@ -159,6 +159,7 @@ static void openrisc_cpu_class_init(ObjectClass *oc, void *data) cc->get_phys_page_debug = openrisc_cpu_get_phys_page_debug; dc->vmsd = &vmstate_openrisc_cpu; #endif + cc->gdb_num_core_regs = 32 + 3; } static void cpu_register(const OpenRISCCPUInfo *info) |