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author | Andreas Färber <afaerber@suse.de> | 2013-05-27 01:33:50 +0200 |
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committer | Andreas Färber <afaerber@suse.de> | 2013-06-28 13:25:12 +0200 |
commit | 878096eeb278a8ac1ccd6667af73e026f29b4cf5 (patch) | |
tree | 1f2ad77025073e5d4b13de7a1df63772d7915ced /target-openrisc | |
parent | 13618e058cf2d76bccc41251fa0095aae88a8249 (diff) | |
download | qemu-878096eeb278a8ac1ccd6667af73e026f29b4cf5.tar.gz qemu-878096eeb278a8ac1ccd6667af73e026f29b4cf5.tar.bz2 qemu-878096eeb278a8ac1ccd6667af73e026f29b4cf5.zip |
cpu: Turn cpu_dump_{state,statistics}() into CPUState hooks
Make cpustats monitor command available unconditionally.
Prepares for changing kvm_handle_internal_error() and kvm_cpu_exec()
arguments to CPUState.
Signed-off-by: Andreas Färber <afaerber@suse.de>
Diffstat (limited to 'target-openrisc')
-rw-r--r-- | target-openrisc/cpu.c | 1 | ||||
-rw-r--r-- | target-openrisc/cpu.h | 2 | ||||
-rw-r--r-- | target-openrisc/translate.c | 12 |
3 files changed, 10 insertions, 5 deletions
diff --git a/target-openrisc/cpu.c b/target-openrisc/cpu.c index f8703a0418..a401706404 100644 --- a/target-openrisc/cpu.c +++ b/target-openrisc/cpu.c @@ -149,6 +149,7 @@ static void openrisc_cpu_class_init(ObjectClass *oc, void *data) cc->class_by_name = openrisc_cpu_class_by_name; cc->do_interrupt = openrisc_cpu_do_interrupt; + cc->dump_state = openrisc_cpu_dump_state; device_class_set_vmsd(dc, &vmstate_openrisc_cpu); } diff --git a/target-openrisc/cpu.h b/target-openrisc/cpu.h index aee77692fb..80a82dfdd8 100644 --- a/target-openrisc/cpu.h +++ b/target-openrisc/cpu.h @@ -347,6 +347,8 @@ OpenRISCCPU *cpu_openrisc_init(const char *cpu_model); void cpu_openrisc_list(FILE *f, fprintf_function cpu_fprintf); int cpu_openrisc_exec(CPUOpenRISCState *s); void openrisc_cpu_do_interrupt(CPUState *cpu); +void openrisc_cpu_dump_state(CPUState *cpu, FILE *f, + fprintf_function cpu_fprintf, int flags); void openrisc_translate_init(void); int cpu_openrisc_handle_mmu_fault(CPUOpenRISCState *env, target_ulong address, diff --git a/target-openrisc/translate.c b/target-openrisc/translate.c index 0eafd0296c..c59fd0208d 100644 --- a/target-openrisc/translate.c +++ b/target-openrisc/translate.c @@ -1814,15 +1814,17 @@ void gen_intermediate_code_pc(CPUOpenRISCState *env, gen_intermediate_code_internal(openrisc_env_get_cpu(env), tb, 1); } -void cpu_dump_state(CPUOpenRISCState *env, FILE *f, - fprintf_function cpu_fprintf, - int flags) +void openrisc_cpu_dump_state(CPUState *cs, FILE *f, + fprintf_function cpu_fprintf, + int flags) { + OpenRISCCPU *cpu = OPENRISC_CPU(cs); + CPUOpenRISCState *env = &cpu->env; int i; - uint32_t *regs = env->gpr; + cpu_fprintf(f, "PC=%08x\n", env->pc); for (i = 0; i < 32; ++i) { - cpu_fprintf(f, "R%02d=%08x%c", i, regs[i], + cpu_fprintf(f, "R%02d=%08x%c", i, env->gpr[i], (i % 4) == 3 ? '\n' : ' '); } } |