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| author | Peter Maydell <peter.maydell@linaro.org> | 2016-03-16 17:05:58 +0000 |
|---|---|---|
| committer | Peter Maydell <peter.maydell@linaro.org> | 2016-03-16 17:05:58 +0000 |
| commit | 8bfd0550be821cf27d71444e2af350de3c3d2ee3 (patch) | |
| tree | 389a9174e2f86d4cee1e5782c8e38d4be9fcbf1a /target-mips | |
| parent | f09f9bd9fa7ccfc1f2b1e88dd35141b1b118ecb7 (diff) | |
| download | qemu-8bfd0550be821cf27d71444e2af350de3c3d2ee3.tar.gz qemu-8bfd0550be821cf27d71444e2af350de3c3d2ee3.tar.bz2 qemu-8bfd0550be821cf27d71444e2af350de3c3d2ee3.zip | |
target-arm: Implement MRS (banked) and MSR (banked) instructions
Starting with the ARMv7 Virtualization Extensions, the A32 and T32
instruction sets provide instructions "MSR (banked)" and "MRS
(banked)" which can be used to access registers for a mode other
than the current one:
* R<m>_<mode>
* ELR_hyp
* SPSR_<mode>
Implement the missing instructions.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Acked-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
Message-id: 1456762734-23939-1-git-send-email-peter.maydell@linaro.org
Diffstat (limited to 'target-mips')
0 files changed, 0 insertions, 0 deletions