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| author | Petar Jovanovic <petar.jovanovic@imgtec.com> | 2014-01-24 13:45:05 +0100 |
|---|---|---|
| committer | Petar Jovanovic <petar.jovanovic@imgtec.com> | 2014-02-10 16:46:12 +0100 |
| commit | b4160af160ba045e3a25013b4def4a39f09cbb78 (patch) | |
| tree | 81c53bf0b988e8b4f7972d908337ec7f5ba51249 /target-mips/translate_init.c | |
| parent | e527526d355570615533d38236818c759f29d889 (diff) | |
| download | qemu-b4160af160ba045e3a25013b4def4a39f09cbb78.tar.gz qemu-b4160af160ba045e3a25013b4def4a39f09cbb78.tar.bz2 qemu-b4160af160ba045e3a25013b4def4a39f09cbb78.zip | |
target-mips: add support for CP0_Config4
Add CP0_Config4, define rw_bitmask.
Signed-off-by: Petar Jovanovic <petar.jovanovic@imgtec.com>
Reviewed-by: Eric Johnson <eric.johnson@imgtec.com>
Diffstat (limited to 'target-mips/translate_init.c')
| -rw-r--r-- | target-mips/translate_init.c | 9 |
1 files changed, 8 insertions, 1 deletions
diff --git a/target-mips/translate_init.c b/target-mips/translate_init.c index d74a0af106..a0398cdc9a 100644 --- a/target-mips/translate_init.c +++ b/target-mips/translate_init.c @@ -45,6 +45,9 @@ (0 << CP0C3_VEIC) | (0 << CP0C3_VInt) | (0 << CP0C3_SP) | \ (0 << CP0C3_SM) | (0 << CP0C3_TL)) +#define MIPS_CONFIG4 \ +((0 << CP0C4_M)) + /* MMU types, the first four entries have the same layout as the CP0C0_MT field. */ enum mips_mmu_types { @@ -64,6 +67,8 @@ struct mips_def_t { int32_t CP0_Config1; int32_t CP0_Config2; int32_t CP0_Config3; + int32_t CP0_Config4; + int32_t CP0_Config4_rw_bitmask; int32_t CP0_Config6; int32_t CP0_Config7; target_ulong CP0_LLAddr_rw_bitmask; @@ -345,7 +350,9 @@ static const mips_def_t mips_defs[] = (0 << CP0C1_DS) | (3 << CP0C1_DL) | (1 << CP0C1_DA) | (1 << CP0C1_CA), .CP0_Config2 = MIPS_CONFIG2, - .CP0_Config3 = MIPS_CONFIG3, + .CP0_Config3 = MIPS_CONFIG3 | (1 << CP0C3_M), + .CP0_Config4 = MIPS_CONFIG4, + .CP0_Config4_rw_bitmask = 0, .CP0_LLAddr_rw_bitmask = 0, .CP0_LLAddr_shift = 4, .SYNCI_Step = 32, |