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| author | ths <ths@c046a42c-6fe2-441c-8c8c-71466251a162> | 2007-08-26 17:37:23 +0000 |
|---|---|---|
| committer | ths <ths@c046a42c-6fe2-441c-8c8c-71466251a162> | 2007-08-26 17:37:23 +0000 |
| commit | 3ddf0b5cde7c741258487710c40f7318fdcd0f18 (patch) | |
| tree | e106e525e0477c3559ae68c90d28406e7c9890dc /target-mips/translate_init.c | |
| parent | c92843b5dfc1e8f7baace9b7a4eac3e3231ac73e (diff) | |
| download | qemu-3ddf0b5cde7c741258487710c40f7318fdcd0f18.tar.gz qemu-3ddf0b5cde7c741258487710c40f7318fdcd0f18.tar.bz2 qemu-3ddf0b5cde7c741258487710c40f7318fdcd0f18.zip | |
Disable 64-bit instructions on 32-bit CPU, by Aurelien Jarno.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3146 c046a42c-6fe2-441c-8c8c-71466251a162
Diffstat (limited to 'target-mips/translate_init.c')
| -rw-r--r-- | target-mips/translate_init.c | 16 |
1 files changed, 9 insertions, 7 deletions
diff --git a/target-mips/translate_init.c b/target-mips/translate_init.c index 85d5032a2b..d327312e55 100644 --- a/target-mips/translate_init.c +++ b/target-mips/translate_init.c @@ -86,7 +86,6 @@ static mips_def_t mips_defs[] = .SYNCI_Step = 32, .CCRes = 2, .Status_rw_bitmask = 0x3278FF17, - .SEGBITS = 32, }, { .name = "4KEcR1", @@ -100,7 +99,6 @@ static mips_def_t mips_defs[] = .SYNCI_Step = 32, .CCRes = 2, .Status_rw_bitmask = 0x3278FF17, - .SEGBITS = 32, }, { .name = "4KEc", @@ -114,7 +112,6 @@ static mips_def_t mips_defs[] = .SYNCI_Step = 32, .CCRes = 2, .Status_rw_bitmask = 0x3278FF17, - .SEGBITS = 32, }, { .name = "24Kc", @@ -128,7 +125,6 @@ static mips_def_t mips_defs[] = .SYNCI_Step = 32, .CCRes = 2, .Status_rw_bitmask = 0x3278FF17, - .SEGBITS = 32, }, { .name = "24Kf", @@ -144,7 +140,6 @@ static mips_def_t mips_defs[] = .Status_rw_bitmask = 0x3678FF17, .CP1_fcr0 = (1 << FCR0_F64) | (1 << FCR0_L) | (1 << FCR0_W) | (1 << FCR0_D) | (1 << FCR0_S) | (0x93 << FCR0_PRID), - .SEGBITS = 32, }, #ifdef TARGET_MIPS64 { @@ -293,8 +288,15 @@ int cpu_mips_register (CPUMIPSState *env, mips_def_t *def) env->Status_rw_bitmask = def->Status_rw_bitmask; env->fcr0 = def->CP1_fcr0; #ifdef TARGET_MIPS64 - env->SEGBITS = def->SEGBITS; - env->SEGMask = (3ULL << 62) | ((1ULL << def->SEGBITS) - 1); + if ((env->CP0_Config0 & (0x3 << CP0C0_AT))) + { + env->hflags |= MIPS_HFLAG_64; + env->SEGBITS = def->SEGBITS; + env->SEGMask = (3ULL << 62) | ((1ULL << def->SEGBITS) - 1); + } else { + env->SEGBITS = 32; + env->SEGMask = 0xFFFFFFFF; + } #endif #ifdef CONFIG_USER_ONLY if (env->CP0_Config1 & (1 << CP0C1_FP)) |