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| author | Edgar E. Iglesias <edgar@axis.com> | 2010-07-24 13:40:05 +0200 |
|---|---|---|
| committer | Edgar E. Iglesias <edgar.iglesias@gmail.com> | 2010-07-24 13:40:05 +0200 |
| commit | fa5f73b1c9730d7ed9c119d1d0ea12df5661cd15 (patch) | |
| tree | 7becf392376dc244c812b5ccd23fd7c227124a0b /target-i386 | |
| parent | 1d4865f5407d07d75e9f2134cf62497ded338b9f (diff) | |
| download | qemu-fa5f73b1c9730d7ed9c119d1d0ea12df5661cd15.tar.gz qemu-fa5f73b1c9730d7ed9c119d1d0ea12df5661cd15.tar.bz2 qemu-fa5f73b1c9730d7ed9c119d1d0ea12df5661cd15.zip | |
mips: Correct MIPS interrupt glue logic for icount
When hw interrupt pending bits in CP0_Cause are set, the CPU should
see the hw interrupt line as active. The CPU may or may not take the
interrupt based on internal state (global irq mask etc) but the glue
logic shouldn't care.
This fixes MIPS external hw interrupts in combination with -icount.
Signed-off-by: Edgar E. Iglesias <edgar@axis.com>
Diffstat (limited to 'target-i386')
0 files changed, 0 insertions, 0 deletions