diff options
| author | Richard Henderson <rth@twiddle.net> | 2013-01-23 16:17:10 -0800 |
|---|---|---|
| committer | Richard Henderson <rth@twiddle.net> | 2013-02-18 15:39:39 -0800 |
| commit | 7073fbada733c8d10992f00772c9b9299d740e9b (patch) | |
| tree | 84a742dbc6dad10feacaa6f586d9ce2341b9116f /target-i386 | |
| parent | 111994ee05b810d81dc6abea7fac5280e48dc198 (diff) | |
| download | qemu-7073fbada733c8d10992f00772c9b9299d740e9b.tar.gz qemu-7073fbada733c8d10992f00772c9b9299d740e9b.tar.bz2 qemu-7073fbada733c8d10992f00772c9b9299d740e9b.zip | |
target-i386: Implement ANDN
As this is the first of the BMI insns to be implemented,
this carries quite a bit more baggage than normal.
Signed-off-by: Richard Henderson <rth@twiddle.net>
Diffstat (limited to 'target-i386')
| -rw-r--r-- | target-i386/cpu.c | 10 | ||||
| -rw-r--r-- | target-i386/translate.c | 19 |
2 files changed, 22 insertions, 7 deletions
diff --git a/target-i386/cpu.c b/target-i386/cpu.c index 0f195337cb..0cb64ab583 100644 --- a/target-i386/cpu.c +++ b/target-i386/cpu.c @@ -406,12 +406,12 @@ typedef struct x86_def_t { #define TCG_EXT3_FEATURES (CPUID_EXT3_LAHF_LM | CPUID_EXT3_SVM | \ CPUID_EXT3_CR8LEG | CPUID_EXT3_ABM | CPUID_EXT3_SSE4A) #define TCG_SVM_FEATURES 0 -#define TCG_7_0_EBX_FEATURES (CPUID_7_0_EBX_SMEP | CPUID_7_0_EBX_SMAP) +#define TCG_7_0_EBX_FEATURES (CPUID_7_0_EBX_SMEP | CPUID_7_0_EBX_SMAP \ + CPUID_7_0_EBX_BMI1 | CPUID_7_0_EBX_BMI2) /* missing: - CPUID_7_0_EBX_FSGSBASE, CPUID_7_0_EBX_BMI1, CPUID_7_0_EBX_HLE, - CPUID_7_0_EBX_AVX2, CPUID_7_0_EBX_BMI2, CPUID_7_0_EBX_ERMS, - CPUID_7_0_EBX_INVPCID, CPUID_7_0_EBX_RTM, CPUID_7_0_EBX_RDSEED, - CPUID_7_0_EBX_ADX */ + CPUID_7_0_EBX_FSGSBASE, CPUID_7_0_EBX_HLE, CPUID_7_0_EBX_AVX2, + CPUID_7_0_EBX_ERMS, CPUID_7_0_EBX_INVPCID, CPUID_7_0_EBX_RTM, + CPUID_7_0_EBX_RDSEED, CPUID_7_0_EBX_ADX */ /* built-in CPU model definitions */ diff --git a/target-i386/translate.c b/target-i386/translate.c index 5a91ff184a..01ff13154d 100644 --- a/target-i386/translate.c +++ b/target-i386/translate.c @@ -2955,8 +2955,9 @@ static const SSEFunc_0_epp sse_op_table1[256][4] = { [0xc6] = { (SSEFunc_0_epp)gen_helper_shufps, (SSEFunc_0_epp)gen_helper_shufpd }, /* XXX: casts */ - [0x38] = { SSE_SPECIAL, SSE_SPECIAL, NULL, SSE_SPECIAL }, /* SSSE3/SSE4 */ - [0x3a] = { SSE_SPECIAL, SSE_SPECIAL }, /* SSSE3/SSE4 */ + /* SSSE3, SSE4, MOVBE, CRC32, BMI1, BMI2, ADX. */ + [0x38] = { SSE_SPECIAL, SSE_SPECIAL, SSE_SPECIAL, SSE_SPECIAL }, + [0x3a] = { SSE_SPECIAL, SSE_SPECIAL, SSE_SPECIAL, SSE_SPECIAL }, /* MMX ops and their SSE extensions */ [0x60] = MMX_OP2(punpcklbw), @@ -4011,6 +4012,20 @@ static void gen_sse(CPUX86State *env, DisasContext *s, int b, } break; + case 0x0f2: /* andn Gy, By, Ey */ + if (!(s->cpuid_7_0_ebx_features & CPUID_7_0_EBX_BMI1) + || !(s->prefix & PREFIX_VEX) + || s->vex_l != 0) { + goto illegal_op; + } + ot = s->dflag == 2 ? OT_QUAD : OT_LONG; + gen_ldst_modrm(env, s, modrm, ot, OR_TMP0, 0); + tcg_gen_andc_tl(cpu_T[0], cpu_regs[s->vex_v], cpu_T[0]); + gen_op_mov_reg_T0(ot, reg); + gen_op_update1_cc(); + set_cc_op(s, CC_OP_LOGICB + ot); + break; + default: goto illegal_op; } |