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| author | Andre Przywara <andre.przywara@amd.com> | 2010-03-11 14:39:03 +0100 |
|---|---|---|
| committer | Aurelien Jarno <aurelien@aurel32.net> | 2010-03-13 16:50:54 +0100 |
| commit | 551a2dec8fa55006a68393b9d6fb63577d2b3f1c (patch) | |
| tree | d6d76dcff7e1343329fd8615a0f7a2510963eaad /target-i386 | |
| parent | 457dfed6146e19e4c7540456533be006076a2307 (diff) | |
| download | qemu-551a2dec8fa55006a68393b9d6fb63577d2b3f1c.tar.gz qemu-551a2dec8fa55006a68393b9d6fb63577d2b3f1c.tar.bz2 qemu-551a2dec8fa55006a68393b9d6fb63577d2b3f1c.zip | |
x86/cpuid: add TCG feature bit trimming
In KVM we trim the user provided CPUID bits to match the host CPU's
one. Introduce a similar feature to QEMU/TCG. Create a mask of TCG's
capabilities and apply it to the user bits.
This allows to let the CPU models reflect their native archetypes.
Signed-off-by: Andre Przywara <andre.przywara@amd.com>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
Diffstat (limited to 'target-i386')
| -rw-r--r-- | target-i386/cpuid.c | 24 |
1 files changed, 24 insertions, 0 deletions
diff --git a/target-i386/cpuid.c b/target-i386/cpuid.c index 635c88e19e..e3dc9e58d0 100644 --- a/target-i386/cpuid.c +++ b/target-i386/cpuid.c @@ -230,6 +230,20 @@ typedef struct x86_def_t { CPUID_PAE | CPUID_SEP | CPUID_APIC) #define EXT2_FEATURE_MASK 0x0183F3FF +#define TCG_FEATURES (CPUID_FP87 | CPUID_PSE | CPUID_TSC | CPUID_MSR | \ + CPUID_PAE | CPUID_MCE | CPUID_CX8 | CPUID_APIC | CPUID_SEP | \ + CPUID_MTRR | CPUID_PGE | CPUID_MCA | CPUID_CMOV | CPUID_PAT | \ + CPUID_PSE36 | CPUID_CLFLUSH | CPUID_ACPI | CPUID_MMX | \ + CPUID_FXSR | CPUID_SSE | CPUID_SSE2 | CPUID_SS) +#define TCG_EXT_FEATURES (CPUID_EXT_SSE3 | CPUID_EXT_MONITOR | \ + CPUID_EXT_CX16 | CPUID_EXT_POPCNT | CPUID_EXT_XSAVE | \ + CPUID_EXT_HYPERVISOR) +#define TCG_EXT2_FEATURES ((TCG_FEATURES & EXT2_FEATURE_MASK) | \ + CPUID_EXT2_NX | CPUID_EXT2_MMXEXT | CPUID_EXT2_RDTSCP | \ + CPUID_EXT2_3DNOW | CPUID_EXT2_3DNOWEXT) +#define TCG_EXT3_FEATURES (CPUID_EXT3_LAHF_LM | CPUID_EXT3_SVM | \ + CPUID_EXT3_CR8LEG | CPUID_EXT3_ABM | CPUID_EXT3_SSE4A) + /* maintains list of cpu model definitions */ static x86_def_t *x86_defs = {NULL}; @@ -792,6 +806,16 @@ int cpu_x86_register (CPUX86State *env, const char *cpu_model) env->cpuid_ext3_features = def->ext3_features; env->cpuid_xlevel = def->xlevel; env->cpuid_kvm_features = def->kvm_features; + if (!kvm_enabled()) { + env->cpuid_features &= TCG_FEATURES; + env->cpuid_ext_features &= TCG_EXT_FEATURES; + env->cpuid_ext2_features &= (TCG_EXT2_FEATURES +#ifdef TARGET_X86_64 + | CPUID_EXT2_SYSCALL | CPUID_EXT2_LM +#endif + ); + env->cpuid_ext3_features &= TCG_EXT3_FEATURES; + } { const char *model_id = def->model_id; int c, len, i; |