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| author | aliguori <aliguori@c046a42c-6fe2-441c-8c8c-71466251a162> | 2008-11-05 15:28:47 +0000 |
|---|---|---|
| committer | aliguori <aliguori@c046a42c-6fe2-441c-8c8c-71466251a162> | 2008-11-05 15:28:47 +0000 |
| commit | 0650f1ab3042f05e9bf8ed9fe3d4dc130b38f162 (patch) | |
| tree | f88ed45f5b9e283da6670909a1bbd5093efb935a /target-i386 | |
| parent | 2c99f7252e355fff8d43072d5c2771b3b16e5899 (diff) | |
| download | qemu-0650f1ab3042f05e9bf8ed9fe3d4dc130b38f162.tar.gz qemu-0650f1ab3042f05e9bf8ed9fe3d4dc130b38f162.tar.bz2 qemu-0650f1ab3042f05e9bf8ed9fe3d4dc130b38f162.zip | |
Add additional CPU flag definitions
Some x86 CPU definitions that KVM needs
Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5625 c046a42c-6fe2-441c-8c8c-71466251a162
Diffstat (limited to 'target-i386')
| -rw-r--r-- | target-i386/cpu.h | 9 |
1 files changed, 8 insertions, 1 deletions
diff --git a/target-i386/cpu.h b/target-i386/cpu.h index 3c11e0f6e9..b1678efd8c 100644 --- a/target-i386/cpu.h +++ b/target-i386/cpu.h @@ -159,9 +159,11 @@ #define HF_MP_MASK (1 << HF_MP_SHIFT) #define HF_EM_MASK (1 << HF_EM_SHIFT) #define HF_TS_MASK (1 << HF_TS_SHIFT) +#define HF_IOPL_MASK (3 << HF_IOPL_SHIFT) #define HF_LMA_MASK (1 << HF_LMA_SHIFT) #define HF_CS64_MASK (1 << HF_CS64_SHIFT) #define HF_OSFXSR_MASK (1 << HF_OSFXSR_SHIFT) +#define HF_VM_MASK (1 << HF_VM_SHIFT) #define HF_SMM_MASK (1 << HF_SMM_SHIFT) #define HF_SVME_MASK (1 << HF_SVME_SHIFT) #define HF_SVMI_MASK (1 << HF_SVMI_SHIFT) @@ -178,6 +180,9 @@ #define HF2_NMI_MASK (1 << HF2_NMI_SHIFT) #define HF2_VINTR_MASK (1 << HF2_VINTR_SHIFT) +#define CR0_PE_SHIFT 0 +#define CR0_MP_SHIFT 1 + #define CR0_PE_MASK (1 << 0) #define CR0_MP_MASK (1 << 1) #define CR0_EM_MASK (1 << 2) @@ -196,7 +201,8 @@ #define CR4_PAE_MASK (1 << 5) #define CR4_PGE_MASK (1 << 7) #define CR4_PCE_MASK (1 << 8) -#define CR4_OSFXSR_MASK (1 << 9) +#define CR4_OSFXSR_SHIFT 9 +#define CR4_OSFXSR_MASK (1 << CR4_OSFXSR_SHIFT) #define CR4_OSXMMEXCPT_MASK (1 << 10) #define PG_PRESENT_BIT 0 @@ -229,6 +235,7 @@ #define PG_ERROR_RSVD_MASK 0x08 #define PG_ERROR_I_D_MASK 0x10 +#define MSR_IA32_TSC 0x10 #define MSR_IA32_APICBASE 0x1b #define MSR_IA32_APICBASE_BSP (1<<8) #define MSR_IA32_APICBASE_ENABLE (1<<11) |